Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Embedded > Microcontrollers

NXP Semiconductors P80CE598FFB/00,518

Name: P80CE598FFB/00,518
Brand: NXP Semiconductors
SKU: P80CE598FFB/00,518
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: P80CE598FFB/00,518

Manufacturer:: NXP Semiconductors

Category:: Microcontrollers

Package:: 80-BQFP

Datasheet:: P80CE598FFB/00,518.pdf

Description:: IC MCU 8BIT ROMLESS 80PQFP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,559

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

P80CE598FFB/00,518 from Philips Semiconductors is an 8-bit microcontroller based on the 80C51 core, featuring an integrated CAN 2.0A controller, 10-bit ADC with 8 analog inputs, dual 8-bit PWM outputs, and 2×256 bytes of on-chip RAM. It operates from 1.2 to 16 MHz, supports −40 to +85 °C industrial temperature range, and targets automotive and industrial networked control systems requiring robust real-time communication.

For engineers reviewing the P80CE598FFB/00,518 datasheet, P80CE598FFB/00,518 pinout, P80CE598FFB/00,518 application, or P80CE598FFB/00,518 equivalent, this device delivers deterministic CAN messaging at up to 1 Mbit/s, hardware-accelerated DMA transfers between CAN buffers and internal RAM, and dedicated analog/digital power domains for EMC-critical environments.

Technical Context

The P80CE598FFB/00,518 integrates a full CAN 2.0A controller with bus failure management, independent CVDD/CVSS power rails, and differential CRX0/CRX1 receiver inputs. Its memory architecture includes 32 kB ROM (external expansion to 64 kB), 512 bytes total on-chip RAM (256-byte MAIN + 256-byte AUXILIARY), and external data memory access via multiplexed AD0–AD7 and A8–A15 buses.

It implements five 8-bit I/O ports plus an 8-bit input-only Port 5 for ADC channels, with programmable alternative functions including CT0I–CT3I capture inputs, CMSR0–CMSR5 compare outputs, and CTX0/CTX1 CAN transmitter pins. Power reduction modes include Idle, Power-down, and CAN Sleep with wake-up capability.

Key Specifications

Parameter	Value and Actual Design Meaning
CPU Core	80C51-compatible 8-bit CPU with standard instruction set and register bank structure.
CAN Interface	On-chip CAN 2.0A controller supporting 1 Mbit/s data rate, bus failure detection, and DMA transfer to internal RAM.
ADC	10-bit successive-approximation ADC with 8 multiplexed analog inputs (ADC0–ADC7) and 37.5 µs conversion time at 16 MHz.
PWM Outputs	Dual 8-bit PWM channels (PWM0/PWM1) with shared 8-bit prescaler and 255-step resolution; push-pull drivers, no function sharing.
Memory	32 kB on-chip ROM (no internal program memory in P80CE598 variant), 512 bytes on-chip RAM (256-byte MAIN + 256-byte AUXILIARY).
Operating Range	−40 to +85 °C ambient temperature; 1.2–16 MHz clock frequency; 5 V supply with separate AVDD/AVSS and CVDD/CVSS rails.
I/O Ports	Six 8-bit parallel ports: P0 (open-drain, AD0–AD7/A0–A7), P1–P4 (quasi-bidirectional), P5 (input-only, ADC0–ADC7).

Pinout & Package

Package: QFP80 (SOT318-1), plastic quad flat package, 80 leads, body size 14 × 20 × 2.7 mm, high stand-off height.

Pin/Terminal	Circuit Role	Design Meaning
VDD1, VDD2, VDD3, VDD4	Digital power supply pins	Four isolated digital VDD rails: VDD1 powers CPU/memory/CAN/UART/ADC logic; VDD2 powers P1/P3/P4/PWM; VDD3 powers oscillator; VDD4 powers P0/P2/ALE/PSEN.
VSS1, VSS2, VSS3, VSS4	Digital ground pins	Corresponding ground pairs for each VDD rail to minimize noise coupling and improve EMC performance.
AVDD / AVSS	Analog power supply	Dedicated +5 V and ground for ADC, CAN receiver, and internal reference voltage generation.
CVDD / CVSS	CAN transmitter power	Isolated +5 V and ground for CAN differential transmitter outputs (CTX0/CTX1) to prevent digital noise injection into CAN bus signals.
CRX0 / CRX1	CAN receiver differential inputs	Differential inputs to on-chip CAN receiver comparator; CRX0 > CRX1 = recessive (logic 1); CRX0 < CRX1 = dominant (logic 0).
CTX0 / CTX1	CAN transmitter outputs	Open-drain differential outputs driving CAN bus; floating during CAN reset; usable as general-purpose open-drain pins when CAN disabled.
P5.0–P5.7	ADC analog inputs	Eight dedicated analog input channels (ADC0–ADC7); Port 5 functions exclusively as input when ADC enabled.
PWM0 / PWM1	PWM output pins	Push-pull, non-multiplexed outputs with 255-step duty cycle control; no alternate functions assigned.
STADC	ADC start trigger	Active-high input that initiates ADC conversion on rising edge; must not be left floating.
REF	1/2AVDD reference output/input	Provides or accepts 1/2AVDD reference voltage for ADC; configured via CAN Control Register bit CR.5.

Key Features

Feature	Design Value
Dedicated CAN power domain	Separate CVDD/CVSS pins isolate CAN transmitter noise from digital logic and analog circuitry, enabling stable 1 Mbit/s operation in noisy automotive environments.
Hardware DMA for CAN	Direct memory access between CAN transmit/receive buffers and internal RAM eliminates CPU overhead during message handling, improving real-time determinism.
Multi-rail digital power architecture	Four independent VDD/VSS pairs per package side reduce simultaneous switching noise and improve electromagnetic compatibility (EMC) radiated emissions by >10 dB.
Configurable ADC reference	Internal 1/2AVDD reference (via REF pin) or external reference selectable in software; eliminates need for external precision voltage reference in cost-sensitive designs.
Flexible timer subsystem	Three 16-bit timers/counters: T0/T1 standard; T2 with four capture latches and three compare registers, enabling precise event timing and PWM synchronization.

Applications

Automotive Body Control Module	Industrial CAN Gateway
Use Scenario: Centralized control of lighting, door locks, window lifts, and HVAC in passenger vehicles using distributed CAN nodes. IC Role / Device Role / Timing Role: Primary CAN node MCU managing sensor inputs (via ADC), actuator PWM outputs (e.g., motor speed), and real-time message routing across multiple CAN subnets. Use Value: Integrated CAN 2.0A controller eliminates external transceiver and interface logic, reducing BOM count and PCB area while ensuring ISO 11898-compliant timing and fault confinement.	Use Scenario: Protocol translation and data aggregation between CAN-based field devices and higher-layer networks (e.g., Ethernet or RS-485) in factory automation. IC Role / Device Role / Timing Role: Dual-role processor executing CAN message filtering, buffering, and retransmission with deterministic latency under 150 µs for critical alarms. Use Value: Hardware DMA offloads CPU during high-throughput CAN traffic (≥500 messages/sec), maintaining UART/SIO0 throughput for host communication without jitter or packet loss.
Off-Highway Vehicle Telematics	Heavy Equipment Diagnostic Node
Use Scenario: Remote monitoring of engine parameters, hydraulic pressure, and GPS location in construction and agricultural machinery operating in harsh EMI environments. IC Role / Device Role / Timing Role: Ruggedized edge node acquiring analog sensor data (temperature, pressure), conditioning signals via 10-bit ADC, and transmitting status over CAN bus with CRC-protected frames. Use Value: Separate AVDD/AVSS and CVDD/CVSS rails maintain ADC accuracy (±1 LSB INL) and CAN signal integrity despite wide-voltage battery transients (−0.5 V to +16 V).	Use Scenario: On-board diagnostics (OBD-II) module reading fault codes, performing active tests, and logging events in diesel-powered generators and compressors. IC Role / Device Role / Timing Role: Standalone diagnostic controller with watchdog (T3), power-down mode for low-quiescent-current sleep (<10 µA), and CAN wake-up on bus activity. Use Value: CAN Sleep Mode enables immediate wake-on-CAN without external interrupt circuitry, reducing system standby power by >95% versus always-on polling architectures.

Automotive Body Control Module

Industrial CAN Gateway

Use Scenario: Centralized control of lighting, door locks, window lifts, and HVAC in passenger vehicles using distributed CAN nodes.

IC Role / Device Role / Timing Role: Primary CAN node MCU managing sensor inputs (via ADC), actuator PWM outputs (e.g., motor speed), and real-time message routing across multiple CAN subnets.

Use Value: Integrated CAN 2.0A controller eliminates external transceiver and interface logic, reducing BOM count and PCB area while ensuring ISO 11898-compliant timing and fault confinement.

Use Scenario: Protocol translation and data aggregation between CAN-based field devices and higher-layer networks (e.g., Ethernet or RS-485) in factory automation.

IC Role / Device Role / Timing Role: Dual-role processor executing CAN message filtering, buffering, and retransmission with deterministic latency under 150 µs for critical alarms.

Use Value: Hardware DMA offloads CPU during high-throughput CAN traffic (≥500 messages/sec), maintaining UART/SIO0 throughput for host communication without jitter or packet loss.

Off-Highway Vehicle Telematics

Heavy Equipment Diagnostic Node

Use Scenario: Remote monitoring of engine parameters, hydraulic pressure, and GPS location in construction and agricultural machinery operating in harsh EMI environments.

IC Role / Device Role / Timing Role: Ruggedized edge node acquiring analog sensor data (temperature, pressure), conditioning signals via 10-bit ADC, and transmitting status over CAN bus with CRC-protected frames.

Use Value: Separate AVDD/AVSS and CVDD/CVSS rails maintain ADC accuracy (±1 LSB INL) and CAN signal integrity despite wide-voltage battery transients (−0.5 V to +16 V).

Use Scenario: On-board diagnostics (OBD-II) module reading fault codes, performing active tests, and logging events in diesel-powered generators and compressors.

IC Role / Device Role / Timing Role: Standalone diagnostic controller with watchdog (T3), power-down mode for low-quiescent-current sleep (<10 µA), and CAN wake-up on bus activity.

Use Value: CAN Sleep Mode enables immediate wake-on-CAN without external interrupt circuitry, reducing system standby power by >95% versus always-on polling architectures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller-with-integrated-CAN applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
NXP SJA1000T	Standalone CAN controller (no CPU, no ADC, no PWM); requires external microcontroller and interface logic (e.g., 80C51).	Used only as CAN peripheral; cannot replace P80CE598FFB/00,518 in monolithic control designs requiring integrated processing.	Select when CAN functionality must be decoupled from main MCU for redundancy or legacy architecture reuse.
Infineon C505CA	8-bit C500-family MCU with CAN 2.0B support, 32 kB ROM, 1 kB RAM, but no integrated ADC or PWM; different instruction set and memory map.	Lacks analog acquisition and motor control peripherals; requires external ADC and PWM ICs for sensor/motor interfaces.	Choose for CAN 2.0B extended frame support and higher RAM, accepting added component count and layout complexity.

Compared with NXP SJA1000T and Infineon C505CA, the P80CE598FFB/00,518 uniquely combines CAN 2.0A, 10-bit ADC, dual PWM, and 80C51 compatibility in a single QFP80 package-enabling compact, low-component-count designs for cost-sensitive industrial and automotive nodes where mixed-signal integration is critical.

Availability

P80CE598FFB/00,518 is available at Aetrix Electronics and suitable for automotive body control modules, industrial CAN gateways, off-highway telematics units, and heavy equipment diagnostic nodes requiring stable component supply across extended product lifecycles.

Supply support for P80CE598FFB/00,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Philips Semiconductors (now NXP Semiconductors) is a global semiconductor leader founded in the Netherlands, specializing in automotive, industrial, and connectivity solutions with emphasis on reliability and system-level integration.

The P8xCE598 product line was designed specifically for automotive and industrial real-time control applications requiring embedded CAN networking, analog sensing, and deterministic timing-addressing the need for single-chip solutions that reduce system complexity and EMI susceptibility.

FAQ

What is the memory configuration of the P80CE598FFB/00,518?

The P80CE598FFB/00,518 contains no on-chip ROM (it is the "without ROM" version), 512 bytes of on-chip RAM (256-byte MAIN RAM + 256-byte AUXILIARY RAM), and supports external program memory up to 64 kB and external data memory up to 64 kB. The P80CE598FFB/00,518 relies on external ROM or flash for program storage, distinguishing it from the P83CE598 variant which includes 32 kB ROM.

Does the P80CE598FFB/00,518 support CAN 2.0B or only CAN 2.0A?

The P80CE598FFB/00,518 implements CAN 2.0A protocol only, supporting standard 11-bit identifiers and data frames up to 8 bytes. It does not support extended 29-bit identifiers defined in CAN 2.0B. This is explicitly confirmed in Section 13.6 of the datasheet titled "CAN 2.0A Protocol description", and the P80CE598FFB/00,518's CAN controller lacks the ID extension logic required for 2.0B compliance.

How is the ADC reference voltage configured on the P80CE598FFB/00,518?

The P80CE598FFB/00,518 provides an internal 1/2AVDD reference voltage accessible via the REF pin (pin 78), configurable through CAN Control Register bit CR.5. When enabled, REF outputs 1/2AVDD; when disabled, it accepts an external reference. A ≥10 nF capacitor must connect REF to AVSS if using the internal reference. This configuration is documented in Table 1, Note 6, and Section 10 of the datasheet.

Can the PWM outputs of the P80CE598FFB/00,518 drive external MOSFETs directly?

Yes-the P80CE598FFB/00,518 PWM0 and PWM1 pins use push-pull drivers with sufficient sink/source current (per DC characteristics table) to directly drive logic-level MOSFET gates or small-signal loads. They are not shared with other functions and operate independently of the prescaler and counter shared between channels. However, for high-side or high-current switching, external gate drivers remain recommended per application requirements.

What is the purpose of the separate CVDD and CVSS pins on the P80CE598FFB/00,518?

The CVDD and CVSS pins provide dedicated power and ground exclusively for the CAN transmitter outputs (CTX0 and CTX1). This isolation prevents digital switching noise from the CPU, timers, or I/O ports from coupling into the CAN differential signals-ensuring clean 1 Mbit/s bus signaling and compliance with ISO 11898 electromagnetic immunity requirements. Their placement as a pin pair on one side of the QFP80 package further minimizes loop area and radiation.

P80CE598FFB/00,518 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Package/Case:: 80-BQFP

Series:: 80C

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Core Processor:: 8051

Core Size:: 8-Bit

Speed:: 16MHz

Connectivity:: CANbus, EBI/EMI, UART/USART

Peripherals:: DMA, POR, PWM, WDT

Number of I/O:: 48

Program Memory Size:: -

Program Memory Type:: ROMless

EEPROM Size:: -

RAM Size:: 512 x 8

Voltage - Supply (Vcc/Vdd):: 4.5V ~ 5.5V

Data Converters:: A/D 8x10b

Oscillator Type:: Internal

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:

P80CE598FFB/00,518 FAQ

1.How can I place an order for P80CE598FFB/00,518 through Aetrix?

Please submit a Request for Quotation (RFQ) for P80CE598FFB/00,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for P80CE598FFB/00,518 reliable?

The price and inventory of P80CE598FFB/00,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P80CE598FFB/00,518 is usually 5 days.

3.What payment methods are accepted for P80CE598FFB/00,518?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P80CE598FFB/00,518 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for P80CE598FFB/00,518?

P80CE598FFB/00,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your P80CE598FFB/00,518 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for P80CE598FFB/00,518?

For technical support, including P80CE598FFB/00,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P80CE598FFB/00,518 requirements.

6.How does Aetrix verify that P80CE598FFB/00,518 is sourced from the original manufacturer or authorized distributors?

All P80CE598FFB/00,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P80CE598FFB/00,518 meets industry standards.

7.What is the process for return or replacement of P80CE598FFB/00,518?

All P80CE598FFB/00,518 units undergo pre-shipment inspection (PSI). If there is an issue with P80CE598FFB/00,518, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The P80CE598FFB/00,518 part is unused and in its original packaging.

Return procedure for P80CE598FFB/00,518:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…