My Inquiry
My Account
NXP Semiconductors P87C51SBPN,112
- Part No.:
- P87C51SBPN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 40-DIP (0.600", 15.24mm)
- Datasheet:
-
P87C51SBPN,112.pdf
- Description:
- IC MCU 8BIT 4KB OTP 40DIP
- Quantity:
- Payment:
- Shipping:
Inventory:3,685
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
P87C51SBPN,112 from Philips Semiconductors is an 8-bit OTP-based microcontroller in the 80C51 architecture family, featuring 4 K × 8 on-chip OTP memory, 128 × 8 RAM, three 16-bit timers/counters, and a full-duplex UART. It operates across 2.7 V–5.5 V at up to 16 MHz and supports idle and power-down modes for low-power embedded control in industrial instrumentation and legacy automation systems.
For engineers reviewing the P87C51SBPN,112 datasheet, P87C51SBPN,112 pinout, P87C51SBPN,112 application, or P87C51SBPN,112 equivalent, this page delivers verified technical context, package-validated pin functions, real-world use scenarios, and two confirmed alternative parts with documented functional and application-level differences.
Technical Context
The P87C51SBPN,112 implements a static CMOS 8051 CPU core with full backward compatibility to MCS-51 instruction set, supporting zero-frequency operation and software-selectable power modes. Its memory subsystem includes 4 K × 8 OTP program memory and 128 × 8 internal RAM, with external addressing capability up to 64 KB ROM and 64 KB RAM via multiplexed Port 0 and Port 2.
It integrates a six-source, four-priority nested interrupt controller, dual data pointers, programmable clock-out on P1.0, and enhanced UART with framing error detection and automatic address recognition. Timer 2 supports capture, auto-reload (up/down), and baud-rate generation - independent of Timer 0/1 - enabling simultaneous serial communication and precise timing tasks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8051-compatible 8-bit CPU with Boolean processor and full static operation down to 0 Hz. |
| Program Memory | 4 K × 8 OTP - non-volatile, one-time programmable memory for firmware storage without external EPROM. |
| RAM Size | 128 × 8 bytes internal RAM - sufficient for small real-time control stacks and data buffers. |
| Max Operating Frequency | 16 MHz at 2.7–5.5 V - enables 1 µs instruction cycle time for deterministic timing-critical tasks. |
| Power Modes | Idle mode (CPU halted, peripherals active) and power-down mode (oscillator stopped, RAM retained) - reduces system power consumption in battery-backed or energy-constrained designs. |
| Serial Interface | Full-duplex UART with framing error detection and automatic address recognition - supports multi-drop RS-485 networks and protocol-aware communication. |
| I/O Ports | Four 8-bit bidirectional ports (P0–P3), each with Schmitt-trigger inputs and internal pull-ups (P1/P2/P3); P0 doubles as AD0–AD7 multiplexed address/data bus. |
Pinout & Package
Package: Plastic Dual In-line Package (PDIP), 40-pin, SOT129-1, commercial temperature range (0 °C to +70 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 40) | Power supply input | Supplies 2.7–5.5 V to entire chip; must be decoupled locally to ensure stable operation during high-current transitions. |
| VSS (Pin 20) | Ground reference | 0 V return path for all digital and analog circuitry; requires low-impedance connection to minimize noise coupling. |
| P0.0–P0.7 (Pins 32–39) | Multiplexed I/O / AD0–AD7 | Open-drain port used as low-order address/data bus during external memory access; requires external pull-ups for reliable logic-high output. |
| P1.0–P1.7 (Pins 1–8) | General-purpose I/O | Bidirectional port with internal pull-ups; P1.0 supports programmable clock-out (61 Hz–4 MHz), P1.1 serves as T2EX for Timer 2 capture/reload control. |
| P2.0–P2.7 (Pins 21–28) | High-order address / A8–A15 | Outputs upper address byte during external memory fetches; also functions as general I/O when no external memory is used. |
| P3.0–P3.7 (Pins 10–17) | Secondary function I/O | Dedicated roles: RxD/TxD (serial), INT0/INT1 (level-sensitive interrupts), T0/T1 (timer inputs), WR/RD (external memory strobes). |
| RST (Pin 9) | Reset input | Active-high reset requiring ≥2 machine cycles (24 oscillator periods); internal weak pull-down enables power-on reset with external RC network. |
| XTAL1/XTAL2 (Pins 19/18) | Oscillator interface | Connects to quartz crystal (1–16 MHz) or external clock source; XTAL1 is input, XTAL2 is output of on-chip inverting amplifier. |
| EA/VPP (Pin 31) | External access enable | High = execute from internal OTP; low = fetch code from external memory starting at 0000H - enables hybrid memory configurations. |
| ALE/PROG (Pin 30) | Address latch enable | Outputs 1/6 oscillator frequency for latching P0 address bits; doubles as programming pulse input during OTP verification. |
| PSEN (Pin 29) | Program store enable | Active-low strobe for external program memory reads; inactive during internal code execution - prevents spurious external accesses. |
Key Features
| Feature | Design Value |
|---|---|
| OTP Program Memory | 4 K × 8 one-time programmable memory eliminates need for external EPROM and simplifies production programming flow. |
| Timer 2 with Capture/Auto-reload | Independent 16-bit timer supporting input capture, up/down counting, and baud-rate generation - enables precise event timing without consuming Timer 0/1 resources. |
| Programmable Clock-Out on P1.0 | Configurable 50% duty-cycle clock output (61 Hz–4 MHz at 16 MHz system clock) provides synchronous timing signal for external logic or ADC sampling. |
| Low EMI Design | Configurable ALE inhibit and slew-rate controlled outputs reduce radiated emissions - critical for compliance in industrial and medical environments. |
| Security Bits & Encryption Array | Three OTP security bits and 64-byte encryption array prevent unauthorized firmware readout - protects intellectual property in deployed devices. |
Applications
| Industrial PLC I/O Module | Legacy Automotive Body Controller |
|---|---|
Use Scenario: Standalone digital input/output expansion module interfacing with Modbus RTU over RS-485 in factory floor control cabinets. IC Role / Device Role / Timing Role: Primary MCU executing ladder logic interpreter, managing 16-channel opto-isolated inputs and relay drivers, and handling UART-based protocol stack. Use Value: Internal 4 K OTP stores hardened firmware; Timer 2 generates precise 9600 baud rate while Timer 0 handles scan cycle timing - no external timing components required. |
Use Scenario: Door lock/unlock and window lift control unit in pre-2005 vehicle platforms with discrete wiring harnesses and no CAN bus. IC Role / Device Role / Timing Role: Central controller reading switch inputs, driving motor drivers via PWM, and communicating status via LIN-compatible UART. Use Value: Power-down mode reduces quiescent current to <10 µA during vehicle sleep; internal RAM retains door position state across ignition cycles without backup capacitor. |
| Medical Infusion Pump Controller | Point-of-Sale Terminal Keypad Interface |
Use Scenario: Safety-critical dosing controller validating stepper motor step counts, monitoring occlusion pressure sensors, and logging events to EEPROM. IC Role / Device Role / Timing Role: Real-time task scheduler with watchdog supervision, managing sensor polling, motor control, and non-volatile data logging. Use Value: Four priority-level interrupts allow immediate response to emergency stop signals; dual data pointer accelerates EEPROM block writes without CPU overhead. |
Use Scenario: Matrix keypad scanner and display driver for cash register terminals using 4×4 keypads and 16-segment LED displays. IC Role / Device Role / Timing Role: Dedicated I/O manager scanning rows/columns, debouncing keys in firmware, and updating display segments via multiplexed Port 0/2. Use Value: Schmitt-trigger inputs on all ports tolerate noisy mechanical switch bounce; programmable clock-out synchronizes display refresh with external LED driver ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT89C51-24PU | 4 K Flash (1,000 write/erase cycles) vs. OTP; same 8051 core, 128 B RAM, 16 MHz max; lacks Timer 2 and programmable clock-out. | Supports field firmware updates; unsuitable where tamper-proof firmware is required or where Timer 2 functionality is essential. | Select AT89C51-24PU only if reprogrammability outweighs security and advanced timing needs. |
| STC89C52RC-PD | 8 K Flash, 256 B RAM, built-in ISP bootloader, 33 MHz max; adds PCA module and enhanced UART but differs in SFR mapping and reset behavior. | Enables in-system programming and higher throughput; requires firmware adaptation due to non-identical peripheral registers and interrupt vectors. | Choose STC89C52RC-PD for new designs needing upgrade path and higher performance, not drop-in replacement. |
Compared with P87C51SBPN,112, AT89C51-24PU trades OTP security for field-upgradable Flash but loses Timer 2 precision, while STC89C52RC-PD offers greater memory and speed at the cost of architectural divergence - making P87C51SBPN,112 optimal for legacy-compliant, security-sensitive, and timing-deterministic deployments.
Availability
P87C51SBPN,112 is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy automotive body controllers, medical infusion pump controllers, and point-of-sale terminal keypad interfaces requiring stable component supply and long-term obsolescence management.
Supply support for P87C51SBPN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Philips Semiconductors (now NXP Semiconductors) is a pioneer in integrated circuit design, delivering high-reliability, industry-standard silicon for automotive, industrial, and consumer applications since the 1970s.
The 80C51/87C51 family was engineered for cost-sensitive, low-power embedded control where 8051 compatibility, OTP security, and deterministic real-time behavior were essential - targeting instrumentation, building automation, and legacy automotive subsystems.
FAQ
What is the maximum operating frequency of the P87C51SBPN,112?
The P87C51SBPN,112 supports a maximum operating frequency of 16 MHz when powered at 2.7–5.5 V. This corresponds to a 1 µs instruction cycle time for single-cycle 8051 instructions. Operation above 16 MHz is not supported - unlike the 'U' variant (e.g., P87C51UBPN), which is rated for 33 MHz at 5 V only.
Does the P87C51SBPN,112 include internal RAM, and how much is available?
Yes, the P87C51SBPN,112 includes 128 × 8 bytes of internal RAM, mapped into the lower 128 bytes of the internal data space (addresses 00H–7FH). This RAM is fully accessible during idle mode and retained in power-down mode down to 2.0 V, enabling state preservation across low-power states without external backup.
Can the P87C51SBPN,112 execute code from external memory?
Yes, the P87C51SBPN,112 can execute code from external program memory when the EA/VPP pin (Pin 31) is held low. In this configuration, it fetches instructions from external ROM/EPROM starting at address 0000H. When EA is high, it executes from internal 4 K OTP, except when the program counter exceeds 0FFFH - then it automatically accesses external memory.
What power-saving modes does the P87C51SBPN,112 support?
The P87C51SBPN,112 supports two software-controlled power-saving modes: Idle mode halts the CPU while preserving RAM, timers, UART, and interrupt logic; Power-down mode stops the oscillator and reduces current to <50 µA, retaining RAM contents. Wake-up from power-down is possible via hardware reset or level-sensitive INT0/INT1 when WUPD bit is enabled.
Is the P87C51SBPN,112 pin-compatible with other 8051-family microcontrollers?
The P87C51SBPN,112 uses the standard 40-pin DIP footprint defined by the 8051 architecture and is pin-compatible with other members of the 80C51/87C51 family in the same package (e.g., P80C51SBPN, P87C52SBPN). However, it is not pin-compatible with Flash-based variants like AT89C51 that repurpose certain pins for programming interfaces.
P87C51SBPN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 40-DIP (0.600", 15.24mm)
- Series:
- 87C
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 16MHz
- Connectivity:
- EBI/EMI, UART/USART
- Peripherals:
- POR
- Number of I/O:
- 32
- Program Memory Size:
- 4KB (4K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 128 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P87C51SBPN,112 FAQ
1.How can I place an order for P87C51SBPN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87C51SBPN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P87C51SBPN,112 reliable?
The price and inventory of P87C51SBPN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87C51SBPN,112 is usually 5 days.
3.What payment methods are accepted for P87C51SBPN,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P87C51SBPN,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P87C51SBPN,112?
P87C51SBPN,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P87C51SBPN,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P87C51SBPN,112?
For technical support, including P87C51SBPN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87C51SBPN,112 requirements.
6.How does Aetrix verify that P87C51SBPN,112 is sourced from the original manufacturer or authorized distributors?
All P87C51SBPN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87C51SBPN,112 meets industry standards.
7.What is the process for return or replacement of P87C51SBPN,112?
All P87C51SBPN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P87C51SBPN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87C51SBPN,112 part is unused and in its original packaging.
Return procedure for P87C51SBPN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
P87C51SBPN,112 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
