NXP Semiconductors P87C51SFPN,112
- Part No.:
- P87C51SFPN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 40-DIP (0.600", 15.24mm)
- Datasheet:
-
P87C51SFPN,112.pdf
- Description:
- IC MCU 8BIT 4KB OTP 40DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P87C51SFPN,112 from Philips Semiconductors is an 8-bit OTP-based microcontroller in the 80C51 architecture family, featuring 4 K × 8 on-chip OTP memory, 128 × 8 RAM, four 8-bit I/O ports, three 16-bit counter/timers, and a full-duplex UART. It operates across –40 °C to +85 °C at 2.7–5.5 V supply, supports idle and power-down modes, and is packaged in a 40-pin plastic DIP (SOT129-1). It serves as a core control unit in industrial sensor interfaces and legacy embedded instrumentation.
For engineers reviewing the P87C51SFPN,112 datasheet, P87C51SFPN,112 pinout, P87C51SFPN,112 application, or P87C51SFPN,112 equivalent, this page delivers verified functional identity, validated pin roles, confirmed low-voltage operation (2.7–5.5 V), real-time power management (idle/power-down), and precise OTP/ROM memory mapping - all essential for legacy system maintenance and drop-in replacement planning.
Technical Context
The P87C51SFPN,112 implements a static CMOS 8051 CPU core with full backward compatibility to MCS-51 instruction set, supporting zero-frequency stop-clock operation and Boolean bit manipulation. Its memory subsystem includes 4 KB of one-time-programmable (OTP) ROM and 128 bytes of on-chip RAM, with external program/data memory access via multiplexed Port 0 (AD0–AD7) and Port 2 (A8–A15).
It integrates a six-source, four-priority nested interrupt controller, programmable clock-out on P1.0 (61 Hz–4 MHz at 16 MHz oscillator), and Timer 2 configured for capture, auto-reload, or baud-rate generation - all operating under 2.7–5.5 V supply without requiring external voltage translation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8051-compatible 8-bit CPU with Boolean processor and full static operation down to 0 MHz |
| Memory | 4 K × 8 OTP ROM + 128 × 8 RAM - enables self-contained firmware execution without external boot ROM |
| Supply Voltage | 2.7 V to 5.5 V - supports direct interface with 3.3 V and 5 V logic domains without level shifters |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial-grade environmental resilience |
| Max Clock Frequency | 16 MHz - defines maximum instruction throughput (1 MIPS per MHz) and UART baud rate ceiling |
| I/O Ports | Four 8-bit bidirectional ports (P0–P3) with Schmitt-trigger inputs and internal pull-ups on P1/P2/P3 |
| Timer/Counter Resources | Three 16-bit timers/counters (T0, T1, T2) - T2 supports capture, reload, and independent baud-rate generation |
Pinout & Package
Package: 40-pin Plastic Dual In-line Package (DIP), SOT129-1, through-hole mountable with 0.6-inch width and standard 0.1-inch pin pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 40) | Power supply input | Primary 2.7–5.5 V supply rail; powers all internal logic, RAM, and I/O drivers |
| VSS (Pin 20) | Ground reference | 0 V return path; must be low-impedance to prevent noise coupling into analog-sensitive peripherals |
| P0.0–P0.7 (Pins 32–39) | Multiplexed address/data bus | Open-drain outputs during external memory access; require external pull-ups; serve as AD0–AD7 and A0–A7 |
| P1.0–P1.7 (Pins 1–8) | General-purpose I/O port | Bidirectional with internal pull-ups; P1.0 supports programmable clock-out; P1.1 supports T2EX capture/reload control |
| P2.0–P2.7 (Pins 21–28) | High-order address bus / I/O | Outputs A8–A15 during external memory fetches; functions as general I/O when no external memory is used |
| P3.0–P3.7 (Pins 10–17) | Secondary function port | Dedicated roles: RxD/TxD (serial), INT0/INT1 (interrupts), T0/T1 (timer inputs), WR/RD (memory strobes) |
| RST (Pin 9) | Active-high reset input | Requires ≥2 machine cycles (24 oscillator periods) high pulse; enables power-on reset with RC network |
| XTAL1 (Pin 19) | Oscillator input | Connects to crystal or external clock source; drives internal inverting amplifier for system timing |
| XTAL2 (Pin 18) | Oscillator output | Drives crystal in parallel-resonant configuration; left unconnected when using external clock on XTAL1 |
| EA/VPP (Pin 31) | External access enable / programming voltage | Low = execute from external ROM; high = execute from internal OTP; receives 12.75 V during OTP programming |
| ALE/PROG (Pin 30) | Address latch enable / programming pulse | Outputs 1/6 oscillator frequency for external latch timing; acts as PROG pulse during OTP programming |
| PSEN (Pin 29) | Program store enable | Active-low read strobe for external program memory; inactive during internal code execution |
Key Features
| Feature | Design Value |
|---|---|
| Full static CMOS design | Enables zero-frequency operation and deterministic wake-up from idle mode without clock stabilization delay |
| Two software-selectable power modes | Idle mode preserves RAM/timers/UART while halting CPU; power-down mode stops oscillator and reduces current to µA range |
| Programmable clock-out on P1.0 | Generates 50% duty-cycle square wave (61 Hz–4 MHz at 16 MHz) for synchronizing external logic or ADC sampling |
| Timer 2 with capture/reload/baud-rate modes | Supports precise event timestamping, PWM generation, and independent UART baud-rate control (separate from Timer 1) |
| Four-level priority interrupt structure | Allows nested servicing of up to six interrupt sources (INT0, INT1, T0, T1, serial, T2) without external arbitration logic |
| Security bits and encryption array | Three OTP security bits prevent unauthorized readout; 64-byte encryption array deters firmware reverse engineering |
Applications
| Industrial Sensor Interface | Legacy PLC I/O Module |
|---|---|
|
Use Scenario: Reads analog sensor outputs via external ADC, performs linearization and scaling, and transmits data over RS-485. IC Role / Device Role / Timing Role: Central controller managing ADC timing, UART framing, and watchdog supervision. Use Value: On-chip 128 B RAM buffers sampled data; idle mode extends battery life in remote nodes; UART supports multi-drop communication. |
Use Scenario: Monitors discrete inputs (limit switches, buttons), drives relay outputs, and communicates status to master controller. IC Role / Device Role / Timing Role: Real-time I/O coordinator with deterministic interrupt latency for safety-critical response. Use Value: Four 8-bit I/O ports provide 32 configurable lines; T0/T1 timers generate precise output pulse widths; –40 °C to +85 °C rating ensures field reliability. |
| Embedded Instrumentation Front-End | Motor Control Sequencer |
|
Use Scenario: Controls display backlight, reads keypad matrix, logs events to EEPROM, and handles USB-to-serial bridge protocol. IC Role / Device Role / Timing Role: System manager handling human interface, nonvolatile storage, and host communication timing. Use Value: Full-duplex UART with framing error detection ensures robust PC communication; internal OTP stores calibration constants securely. |
Use Scenario: Generates commutation signals for 3-phase BLDC motor using timer compare outputs and monitors hall-effect sensors. IC Role / Device Role / Timing Role: Timing-critical sequencer coordinating PWM generation, sensor sampling, and fault shutdown. Use Value: Timer 2 capture mode precisely timestamps hall sensor edges; P3.2/P3.3 interrupts respond to overcurrent within <2 µs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT89C51-24PI | 4 KB Flash (1,000 write/erase cycles) vs. OTP; same 40-pin DIP package; 24 MHz max clock | Field-upgradable firmware required; higher endurance needed for prototyping or frequent updates | Select when reprogrammability and longer development lifecycle outweigh OTP's permanent firmware security |
| STC89C52RC-PD | 8 KB Flash, 512 B RAM, enhanced ISP capability; 5 V only; same pinout but different reset timing and power-down behavior | Higher memory headroom for larger control algorithms; requires updated bootloader and reset circuit design | Select when migrating from legacy 8051 systems needing more RAM/Flash and integrated ISP without external programmer |
Compared with AT89C51-24PI and STC89C52RC-PD, the P87C51SFPN,112 offers guaranteed OTP firmware immutability and industrial temperature support out-of-box, whereas alternatives trade permanence for reprogrammability or memory expansion - making P87C51SFPN,112 optimal for fixed-function, long-lifecycle deployments where firmware integrity is critical.
Availability
P87C51SFPN,112 is available at Aetrix Electronics and suitable for industrial sensor interfaces, legacy PLC I/O modules, and embedded instrumentation front-ends requiring stable component supply, long-term obsolescence management, and guaranteed industrial temperature performance.
Supply support for P87C51SFPN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Philips Semiconductors (now NXP Semiconductors) is a pioneer in mixed-signal IC design, delivering high-reliability components for automotive, industrial, and consumer applications since the 1950s.
The P87C51SFPN,112 belongs to the 80C51/87C51 family - designed specifically for cost-sensitive, low-power embedded control in harsh environments where firmware permanence, wide voltage operation, and proven 8051 compatibility are mandatory.
FAQ
What is the memory configuration of the P87C51SFPN,112?
The P87C51SFPN,112 contains 4 K × 8 one-time-programmable (OTP) ROM for program storage and 128 × 8 bytes of on-chip RAM for data and stack operations. This configuration eliminates the need for external program memory in most standalone applications and supports full 64 KB external addressing when required. The OTP ensures firmware integrity and prevents unauthorized modification after programming.
Does the P87C51SFPN,112 support low-voltage operation?
Yes, the P87C51SFPN,112 operates across a supply voltage range of 2.7 V to 5.5 V, enabling direct integration with both 3.3 V and 5 V system rails without level-shifting circuitry. This dual-voltage capability simplifies power architecture in mixed-signal designs and supports battery-powered operation down to 2.7 V while maintaining full functionality including UART, timers, and I/O drive strength.
How does the power-down mode work on the P87C51SFPN,112?
In power-down mode, the P87C51SFPN,112 stops the oscillator and disables all digital circuitry except RAM and SFRs, reducing current consumption to microamp levels. Wake-up is triggered by either a hardware reset or an enabled external interrupt (INT0 or INT1, configured as level-sensitive). The P87C51SFPN,112 retains RAM contents down to 2.0 V, ensuring state persistence across brownout conditions.
Can the P87C51SFPN,112 generate a precise clock signal for external circuitry?
Yes, the P87C51SFPN,112 supports programmable clock-out on P1.0, delivering a 50% duty-cycle square wave ranging from 61 Hz to 4 MHz (at 16 MHz oscillator). This is achieved by configuring Timer 2 in auto-reload mode with appropriate RCAP2H/RCAP2L values. The feature eliminates the need for external clock generators in synchronous peripheral interfacing such as ADC sampling or logic state machines.
What is the role of the EA/VPP pin on the P87C51SFPN,112?
The EA/VPP pin on the P87C51SFPN,112 serves two functions: External Access Enable (EA) and Programming Supply Voltage (VPP). When EA is high, the P87C51SFPN,112 executes from internal OTP memory; when low, it fetches code from external program memory starting at 0000H. During OTP programming, VPP = 12.75 V is applied to this pin to enable write operations - a requirement strictly enforced by the internal programming logic of the P87C51SFPN,112.
P87C51SFPN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 40-DIP (0.600", 15.24mm)
- Series:
- 87C
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 16MHz
- Connectivity:
- EBI/EMI, UART/USART
- Peripherals:
- POR
- Number of I/O:
- 32
- Program Memory Size:
- 4KB (4K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 128 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P87C51SFPN,112 FAQ
1.How can I place an order for P87C51SFPN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87C51SFPN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P87C51SFPN,112 reliable?
The price and inventory of P87C51SFPN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87C51SFPN,112 is usually 5 days.
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Once your P87C51SFPN,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P87C51SFPN,112?
For technical support, including P87C51SFPN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87C51SFPN,112 requirements.
6.How does Aetrix verify that P87C51SFPN,112 is sourced from the original manufacturer or authorized distributors?
All P87C51SFPN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87C51SFPN,112 meets industry standards.
7.What is the process for return or replacement of P87C51SFPN,112?
All P87C51SFPN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P87C51SFPN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87C51SFPN,112 part is unused and in its original packaging.
Return procedure for P87C51SFPN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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