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NXP Semiconductors P87C52UBPN,112
- Part No.:
- P87C52UBPN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 40-DIP (0.600", 15.24mm)
- Datasheet:
-
P87C52UBPN,112.pdf
- Description:
- IC MCU 8BIT 8KB OTP 40DIP
- Quantity:
- Payment:
- Shipping:
Inventory:3,202
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Product details
Overview
P87C52UBPN,112 from NXP Semiconductors (formerly Philips) is an 8-bit OTP-based microcontroller in the 80C51 architecture family, featuring 8 KB on-chip OTP ROM, 256 B RAM, three 16-bit timers/counters, full-duplex UART with framing error detection, and four 8-bit I/O ports. It operates at up to 33 MHz with 5 V supply and targets embedded control in industrial instrumentation and legacy automation systems.
For engineers reviewing the P87C52UBPN,112 datasheet, P87C52UBPN,112 pinout, P87C52UBPN,112 application, or P87C52UBPN,112 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases, and two confirmed alternative parts - all grounded in the official Philips 2000 product specification.
Technical Context
The P87C52UBPN,112 implements a static CMOS 8051 core with full backward compatibility to MCS-51 instruction set, supporting zero-frequency operation and dual power-saving modes: idle mode (CPU halted, peripherals active) and power-down mode (oscillator stopped, RAM retained down to 2.0 V). Its 33 MHz max frequency at 5 V enables high-throughput serial communication and timer-driven event handling.
It integrates a programmable clock-out function on P1.0 (T2), Timer 2 operating in capture/auto-reload/baud-rate generator modes, and hardware support for multi-processor UART communication via address recognition. The device uses internal pull-ups on Ports 1–3 and open-drain Port 0 with Schmitt-trigger inputs for noise immunity in industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8051-compatible 8-bit CPU with Boolean processor and static design enabling 0 Hz operation |
| Memory | 8 KB × 8 OTP ROM + 256 × 8 RAM - sufficient for standalone firmware without external code memory |
| Max Clock Frequency | 33 MHz at 5 V - supports 115.2 kbps UART at 16× oversampling with precise timing margins |
| I/O Capability | Four 8-bit bidirectional ports (32 lines), with Port 0 multiplexed for external address/data bus access |
| Timer/Counter Resources | Three 16-bit timers: T0/T1 standard, T2 with capture/reload/baud-rate generation and clock-out capability |
| Power Management | Idle and power-down modes; wake-up from power-down via INT0/INT1 with WUPD bit control (AUXR1.3) |
| Serial Interface | Full-duplex UART with framing error detection, automatic address recognition, and dual clock source options (T1 or T2) |
Pinout & Package
Package: Plastic Dual In-line Package (PDIP), 40-pin, SOT129-1, commercial temperature range (0 °C to +70 °C), 5 V only operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 40) | Power supply input | 5 V nominal supply; powers all internal logic and I/O drivers; requires local decoupling |
| VSS (Pin 20) | Ground reference | 0 V return path; must be low-impedance connection to minimize noise coupling into analog-sensitive circuits |
| P0.0–P0.7 (Pins 32–39) | Multiplexed address/data bus | Open-drain outputs requiring external pull-ups; serves as AD0–AD7 during external memory access |
| P1.0/T2 (Pin 1) | General-purpose I/O / Timer 2 clock output | Configurable as 50% duty-cycle clock-out (61 Hz–4 MHz) or external count input for T2 |
| P1.1/T2EX (Pin 2) | Timer 2 control input | Triggers capture/reload events or controls up/down counting direction in auto-reload mode |
| P2.0–P2.7 (Pins 21–28) | High-order address bus / I/O | Outputs A8–A15 during external program/data fetches; retains port functionality when not addressing |
| P3.0/RxD (Pin 10) | Serial receive input | Asynchronous UART input with Schmitt trigger; supports TTL/CMOS-level signals |
| P3.1/TxD (Pin 11) | Serial transmit output | UART output with internal pull-up; compatible with RS-232 level shifters via external driver |
| RST (Pin 9) | Active-high reset input | Requires ≥2 machine cycles (24 oscillator periods) high pulse; internal weak pull-down enables RC-based POR |
| XTAL1 (Pin 19) | Oscillator input | Connects to crystal or external clock source; internal inverting amplifier forms Pierce oscillator |
| XTAL2 (Pin 18) | Oscillator output | Drives crystal; left unconnected when using external clock applied to XTAL1 |
| EA/VPP (Pin 31) | External access enable / programming voltage | Low = execute from external ROM; high = execute from internal OTP; receives 12.75 V during programming |
| ALE/PROG (Pin 30) | Address latch enable / programming pulse | Emits 1/6 oscillator frequency for external latch sync; doubles as EPROM programming pulse |
| PSEN (Pin 29) | Program store enable | Active-low strobe for external program memory reads; inactive during internal code execution |
Key Features
| Feature | Design Value |
|---|---|
| Static CMOS design | Enables true zero-power idle mode and deterministic stop/resume behavior without data loss |
| Programmable clock-out on P1.0 | Generates precise system clocks or timing references for external logic without additional oscillators |
| Timer 2 with capture/reload/baud-rate modes | Eliminates need for external timing ICs in motor control, pulse-width measurement, or dual-baud-rate UART |
| Four priority-level nested interrupt structure | Supports real-time response to six interrupt sources (INT0, INT1, T0, T1, serial, T2) with minimal latency |
| Security bits and encryption array | Three OTP security bits and 64-byte encryption array protect firmware against unauthorized readout |
| Low EMI design | Configurable ALE inhibit and slew-rate-controlled outputs reduce radiated emissions in sensitive EMC environments |
Applications
| Industrial PLC I/O Module | Legacy Serial Communication Gateway |
|---|---|
|
Use Scenario: Standalone I/O expansion node in distributed control systems, interfacing with sensors and actuators via discrete digital signals. IC Role / Device Role / Timing Role: Primary controller executing ladder logic scan cycles, managing 32-bit parallel I/O, and synchronizing with master PLC via RS-485. Use Value: 256 B RAM supports multiple register banks for fast context switching; 33 MHz clock ensures sub-millisecond scan times at 10 kHz polling rates. |
Use Scenario: Protocol translator bridging Modbus RTU devices to ASCII-based host systems in factory floor networks. IC Role / Device Role / Timing Role: UART-centric controller performing frame parsing, CRC calculation, and address mapping between incompatible serial protocols. Use Value: Hardware UART with framing error detection and automatic address recognition reduces firmware overhead by >40% versus bit-banged implementations. |
| Embedded Power Supply Monitor | Legacy Test Equipment Controller |
|
Use Scenario: Real-time monitoring of AC/DC power supply parameters (voltage, current, temperature) with fault logging and LED status indication. IC Role / Device Role / Timing Role: Sensor interface hub collecting analog readings via external ADC, executing safety thresholds, and driving status outputs. Use Value: Three independent 16-bit timers enable simultaneous sampling intervals, watchdog timeout, and LED blink timing without software polling. |
Use Scenario: Front-panel controller for benchtop instruments (e.g., multimeters, signal generators) managing keypad scanning, display updates, and calibration routines. IC Role / Device Role / Timing Role: Human-interface processor coordinating button debounce, 7-segment display multiplexing, and non-volatile parameter storage. Use Value: 8 KB OTP provides ample space for menu navigation logic, character fonts, and calibration coefficients - eliminating need for external EEPROM. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT89C52-24PU | 8 KB Flash (not OTP), 24 MHz max, same 40-pin PDIP package and pinout | Field-upgradable firmware; lacks T2EX capture functionality and programmable clock-out on P1.0 | Select when firmware updates are required in deployed units; verify UART timing margins at 24 MHz vs. 33 MHz |
| STC89C52RC-PDIP40 | 8 KB Flash, 35 MHz max, enhanced ISP capability, but non-identical SFR map and reset behavior | Integrated ISP eliminates need for external programmer; requires firmware porting due to non-Philips SFR layout | Select for new designs prioritizing in-system programming; avoid drop-in replacement without validation |
Compared with AT89C52-24PU and STC89C52RC-PDIP40, the P87C52UBPN,112 offers guaranteed OTP security, precise 33 MHz timing for high-speed UART, and native T2EX capture - making it optimal for fixed-function, tamper-resistant industrial controllers where field updates are unnecessary.
Availability
P87C52UBPN,112 is available at Aetrix Electronics and suitable for industrial PLC modules, legacy serial gateways, embedded power monitors, and test equipment controllers requiring stable component supply and long-term obsolescence management.
Supply support for P87C52UBPN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors, formerly Philips Semiconductors, is a global leader in high-reliability automotive, industrial, and secure connectivity solutions with over 50 years of microcontroller innovation.
The P87C52UBPN,112 belongs to the 80C51/87C52 OTP microcontroller family designed specifically for cost-sensitive, high-volume industrial control applications demanding proven architecture, long-lifecycle support, and robust EMI performance.
FAQ
What is the maximum operating frequency of the P87C52UBPN,112?
The P87C52UBPN,112 supports a maximum operating frequency of 33 MHz at 5 V supply voltage, as specified in the Philips 2000 product specification. This enables precise baud-rate generation for UART communication up to 115.2 kbps with 16× oversampling, and supports tight timing loops in real-time control applications. Operation above 33 MHz is not guaranteed and may result in undefined behavior.
Does the P87C52UBPN,112 support external memory expansion?
Yes, the P87C52UBPN,112 supports external program and data memory expansion via its multiplexed Port 0 (AD0–AD7) and Port 2 (A8–A15), along with dedicated control signals PSEN, ALE, RD, and WR. When EA/VPP is held low, the device fetches code from external program memory; when high, it executes from internal OTP unless the program counter exceeds 0x1FFF. External memory access timing complies with standard 80C51 bus cycles.
How does the power-down mode work on the P87C52UBPN,112?
In power-down mode, the P87C52UBPN,112 stops the oscillator while retaining RAM and SFR contents down to 2.0 V. Wake-up is triggered by hardware reset or enabled external interrupts (INT0/INT1), provided WUPD bit (AUXR1.3) is set. Upon wake-up, execution resumes from the instruction following the one that initiated power-down. Oscillator stabilization time (<10 ms) must elapse before reliable operation resumes.
Can the P87C52UBPN,112 generate a clock signal on P1.0?
Yes, the P87C52UBPN,112 can generate a 50% duty-cycle clock signal on P1.0 (T2) by configuring Timer 2 in clock-out mode: clear C/T2 (T2CON.1), set T2OE (T2MOD.6), and enable TR2 (T2CON.2). The output frequency is determined by the oscillator frequency and RCAP2H/RCAP2L reload value per the formula fCLKOUT = fOSC / [4 × (65536 − RCAP2)]. This eliminates need for external clock generators in synchronized peripheral designs.
What are the security features of the P87C52UBPN,112?
The P87C52UBPN,112 includes three OTP security bits and a 64-byte encryption array to prevent unauthorized firmware readout. Once programmed, these features lock the internal code memory against external verification or copying. Security bit activation is irreversible and requires proper programming voltage (12.75 V on EA/VPP) during OTP programming - a safeguard against accidental exposure of proprietary control algorithms.
P87C52UBPN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 40-DIP (0.600", 15.24mm)
- Series:
- 87C
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 33MHz
- Connectivity:
- EBI/EMI, UART/USART
- Peripherals:
- POR
- Number of I/O:
- 32
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P87C52UBPN,112 FAQ
1.How can I place an order for P87C52UBPN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87C52UBPN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P87C52UBPN,112 reliable?
The price and inventory of P87C52UBPN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87C52UBPN,112 is usually 5 days.
3.What payment methods are accepted for P87C52UBPN,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P87C52UBPN,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P87C52UBPN,112?
P87C52UBPN,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P87C52UBPN,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P87C52UBPN,112?
For technical support, including P87C52UBPN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87C52UBPN,112 requirements.
6.How does Aetrix verify that P87C52UBPN,112 is sourced from the original manufacturer or authorized distributors?
All P87C52UBPN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87C52UBPN,112 meets industry standards.
7.What is the process for return or replacement of P87C52UBPN,112?
All P87C52UBPN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P87C52UBPN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87C52UBPN,112 part is unused and in its original packaging.
Return procedure for P87C52UBPN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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