NXP Semiconductors P87C552SBAA,512
- Part No.:
- P87C552SBAA,512
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
P87C552SBAA,512.pdf
- Description:
- IC MCU 8BIT 8KB OTP 68PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P87C552SBAA,512 from NXP Semiconductors (formerly Philips) is an 8-bit 80C51-compatible microcontroller with 8 KB OTP program memory, 256 B RAM, eight-channel 10-bit ADC, dual PWM outputs, I²C bus interface, and capture/compare timer subsystem. It operates from 2.7 V to 5.5 V at up to 16 MHz and targets embedded control in industrial sensors, motor drive interfaces, and low-power instrumentation.
For engineers reviewing the P87C552SBAA,512 datasheet, P87C552SBAA,512 pinout, P87C552SBAA,512 application, or P87C552SBAA,512 equivalent, this page delivers verified functional architecture, PLCC-68 package mapping, low-voltage power modes, and direct substitution guidance for legacy 8051-based designs requiring analog integration and deterministic timing.
Technical Context
The P87C552SBAA,512 implements a static CMOS 80C51 core with full instruction set compatibility, extended SFRs including AUXR and AUXR1 for dual DPTR and ADC mode control, and hardware-accelerated peripherals: two standard 16-bit timers, one additional 16-bit timer (T2) with four capture latches and three compare registers, and an enhanced UART supporting framing error detection and automatic address recognition.
Its analog subsystem integrates an 8-input, 10-bit successive-approximation ADC with programmable charge pump (LVADC bit), configurable start trigger (STADC pin or software), and optional 8-bit fast conversion mode (ADC8 bit). Power management includes idle mode (CPU halted, peripherals active, ADC operable) and power-down mode (oscillator stopped, RAM retained down to 2.0 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 80C51-compatible 8-bit CPU with 100+ instructions; 58% executed in 0.75 µs at 16 MHz |
| Memory | 8 KB on-chip OTP EPROM; 256 B internal RAM; external memory expansion up to 64 KB via multiplexed bus |
| ADC | 8-channel, 10-bit SAR ADC; supports 8-bit fast mode (24 cycles) or 10-bit precision mode (50 cycles) |
| Timers & PWM | Three 16-bit timers: T0/T1 (standard), T2 (capture/compare with CMSR/CMT outputs); two independent 8-bit PWM outputs |
| I/O & Interfaces | Five 8-bit I/O ports (P0–P4) + dedicated 8-bit input port (P5); I²C-bus master/slave; enhanced UART with FE detection and auto-address recognition |
| Power Modes | Full static operation (0–16 MHz); idle mode (CPU halted, RAM/timers/UART/ADC active); power-down mode (oscillator halted, RAM retained ≥2.0 V) |
| Supply Voltage | 2.7 V to 5.5 V across full 0–16 MHz frequency range; AVDD/AVSS separate analog supply pins |
Pinout & Package
Package: Plastic Leaded Chip Carrier (PLCC), 68-pin, SOT188–3 drawing. Pin 1 = P5.0/ADC0; Pin 68 = P5.1/ADC1 (per official pin configuration diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0–P0.7 (pins 57–50) | Multiplexed Address/Data Bus / I/O | Low-order address/data during external memory access; open-drain I/O with internal pull-ups when used as port |
| P1.0–P1.3 (pins 16–19) | Capture Input Signals | CT0I–CT3I inputs to Timer 2 capture latches; support edge-triggered timestamping of external events |
| P1.4/P1.5 (pins 20/21) | Timer 2 Event Interface | T2 (event input) and RT2 (timer reset) enable precise pulse-width measurement and gated timing windows |
| P1.6/P1.7 (pins 22/23) | I²C Bus Interface | SCL (clock) and SDA (data) pins with open-drain configuration; support multi-master arbitration and slave addressing |
| P4.0–P4.5 (pins 7–12) | Compare Set/Reset Outputs | CMSR0–CMSR5 outputs toggle or set/reset on T2 match; used for synchronized waveform generation and state machine control |
| P5.0–P5.7 (pins 1,68–62) | Analog Input Channels | Dedicated 8-bit input port serving as ADC0–ADC7 analog multiplexer inputs; no digital I/O capability |
| STADC (pin 3) | Hardware ADC Start | Active-low asynchronous trigger for ADC conversion; enables precise timing-critical sampling independent of CPU load |
| PWM0/PWM1 (pins 4/5) | Pulse Width Modulation Outputs | Two independent 8-bit resolution PWM generators; support motor speed control, LED dimming, and DAC-like analog output |
Key Features
| Feature | Design Value |
|---|---|
| Dual Data Pointer (DPTR0/DPTR1) | Enables simultaneous access to two external data memory regions without software-managed register save/restore overhead |
| ADC Low-Voltage Operation (LVADC) | Charge pump activation allows full 10-bit ADC functionality below 4 V supply, critical for battery-powered 3.3 V or 2.7 V systems |
| ALE Inhibit Mode (AO bit) | Disables ALE clock output except during MOVX/MOVC instructions, reducing EMI in noise-sensitive analog or RF-adjacent layouts |
| Software Reset (SRST bit) | Permits controlled system restart without external hardware reset circuitry, enabling firmware self-recovery and field-upgrade safety |
| ONCE™ On-Circuit Emulation | Allows real-time debugging in-system via Port 0 float-state entry; eliminates socket removal and target board rework during development |
Applications
| Industrial Sensor Node | Motor Drive Interface |
|---|---|
|
Use Scenario: Standalone temperature/humidity sensor with local signal conditioning and I²C reporting to host MCU. IC Role / Device Role / Timing Role: Primary controller executing ADC sampling, linearization, and I²C slave communication; uses T2 capture to timestamp sensor events. Use Value: Integrated 10-bit ADC and I²C eliminate external converters and level shifters; low-voltage operation extends battery life in remote deployments. |
Use Scenario: Brushless DC motor commutation controller with Hall-effect feedback and PWM gate drive. IC Role / Device Role / Timing Role: Real-time commutation sequencer using PWM0/PWM1 outputs and P4 CMSR outputs for synchronized phase switching. Use Value: Hardware capture/compare logic ensures sub-microsecond timing accuracy for 6-step commutation; dual DPTR simplifies lookup table access for torque profiles. |
| Programmable Logic Controller I/O Module | Energy Meter Front-End |
|
Use Scenario: DIN-rail mounted I/O expansion module with digital input debouncing and relay output control. IC Role / Device Role / Timing Role: Dedicated I/O processor managing 32+ opto-isolated inputs via P0–P4; uses idle mode to reduce standby power between polling cycles. Use Value: Five full I/O ports plus dedicated input port (P5) provide native 40+ GPIO without external expanders; power-down mode achieves <10 µA sleep current. |
Use Scenario: Residential electricity meter measuring voltage/current waveforms and computing RMS/kWh values. IC Role / Device Role / Timing Role: Analog front-end controller acquiring synchronized voltage/current samples via ADC0–ADC7; uses T2 for precise line-cycle timing. Use Value: 10-bit ADC with LVADC support maintains accuracy across 2.7–5.5 V supply range; enhanced UART enables secure firmware updates over RS-485. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89C51RD2FA,512 | 80C51 core with 64 KB Flash, 1.25 KB RAM, no integrated ADC; same PLCC-68 package and pin-compatible I/O mapping | Lacks on-chip ADC and PWM; requires external analog front-end but offers larger code space and ISP capability | Select when firmware size exceeds 8 KB or field reprogramming is required; not suitable for ADC-dependent designs. |
| AT89C51ED2-RL24 | 8051 derivative with 128 KB Flash, USB interface, and 10-bit ADC; QFP-44 package, non-pin-compatible | Includes USB 2.0 peripheral and higher-speed core (up to 42 MHz); ADC shares pins with general-purpose I/O | Choose for USB-connected devices needing higher throughput; requires PCB redesign due to QFP-44 footprint and different pinout. |
Compared with P87C552SBAA,512, the P89C51RD2FA,512 trades integrated analog capability for flash density and in-system programming, while the AT89C51ED2-RL24 adds USB connectivity at the cost of package compatibility and increased design complexity-making P87C552SBAA,512 optimal for cost-sensitive, analog-rich, fixed-function embedded controllers.
Availability
P87C552SBAA,512 is available at Aetrix Electronics and suitable for industrial sensor nodes, motor drive interfaces, PLC I/O modules, and energy meter front-ends requiring stable component supply and long-term obsolescence management.
Supply support for P87C552SBAA,512 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors acquired Philips Semiconductors in 2006 and continues to support legacy 80C51-based microcontrollers with documentation, reference designs, and cross-qualified replacements.
The P87C552SBAA,512 belongs to the 80C51 derivative family designed for cost-effective, mixed-signal embedded control where analog integration, deterministic timing, and low-voltage operation are essential.
FAQ
What is the maximum operating frequency and voltage range for the P87C552SBAA,512?
The P87C552SBAA,512 operates from 2.7 V to 5.5 V across its full 0–16 MHz frequency range. Its static CMOS design guarantees reliable execution at any frequency within this band, including zero Hz (stopped clock mode), enabling ultra-low-power duty-cycled operation in battery-powered systems.
Does the P87C552SBAA,512 support hardware ADC triggering independent of CPU activity?
Yes, the P87C552SBAA,512 provides dedicated STADC (pin 3) for asynchronous hardware start of ADC conversion. This allows precise, jitter-free sampling aligned to external events-such as motor commutation edges or sensor wake signals-without CPU intervention or instruction cycle latency.
How does the P87C552SBAA,512 handle power-down wake-up from external interrupts?
The P87C552SBAA,512 requires the WUPD bit (AUXR1.3) to be set before entering power-down mode. Once enabled, level-sensitive INT0 or INT1 interrupts can restart the oscillator and resume execution from the instruction following the power-down command, preserving all RAM and SFR contents.
Can the P87C552SBAA,512's I²C interface operate as both master and slave?
Yes, the P87C552SBAA,512's I²C-bus serial port supports full byte-oriented master and slave functions per the Philips specification. Pins P1.6 (SCL) and P1.7 (SDA) implement open-drain signaling with internal pull-up control, enabling bidirectional communication in multi-node sensor networks.
Is the P87C552SBAA,512 pin-compatible with other 80C51 derivatives like the P89C51RB2?
No, the P87C552SBAA,512 is not pin-compatible with the P89C51RB2. While both use PLCC packages, the P87C552SBAA,512 has 68 pins (SOT188–3) with dedicated analog input port (P5) and capture/compare pins (P1.0–P1.5), whereas the P89C51RB2 uses 44-pin QFP and lacks these specialized functions and pin assignments.
P87C552SBAA,512 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 68-LCC (J-Lead)
- Series:
- 87C
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 16MHz
- Connectivity:
- EBI/EMI, I2C, UART/USART
- Peripherals:
- POR, PWM, WDT
- Number of I/O:
- 40
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P87C552SBAA,512 FAQ
1.How can I place an order for P87C552SBAA,512 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87C552SBAA,512 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P87C552SBAA,512 reliable?
The price and inventory of P87C552SBAA,512 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87C552SBAA,512 is usually 5 days.
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5.How can I obtain technical support or documentation for P87C552SBAA,512?
For technical support, including P87C552SBAA,512 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87C552SBAA,512 requirements.
6.How does Aetrix verify that P87C552SBAA,512 is sourced from the original manufacturer or authorized distributors?
All P87C552SBAA,512 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87C552SBAA,512 meets industry standards.
7.What is the process for return or replacement of P87C552SBAA,512?
All P87C552SBAA,512 units undergo pre-shipment inspection (PSI). If there is an issue with P87C552SBAA,512, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87C552SBAA,512 part is unused and in its original packaging.
Return procedure for P87C552SBAA,512:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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