NXP Semiconductors P87C58X2BBD,157
- Part No.:
- P87C58X2BBD,157
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 44-LQFP
- Datasheet:
-
P87C58X2BBD,157.pdf
- Description:
- IC MCU 8BIT 32KB OTP 44LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P87C58X2BBD,157 from Philips Semiconductors is a 32 KB OTP-based 8-bit microcontroller in the 80C51 architecture, featuring 256 B RAM, three 16-bit timers (T0/T1/T2), full-duplex UART with framing error detection, and dual clock modes (6-/12-clock). It operates from 2.7 V to 5.5 V and supports up to 33 MHz at 5 V in 12-clock mode - used in industrial control panels requiring deterministic real-time I/O handling and firmware-upgradable logic.
For engineers reviewing the P87C58X2BBD,157 datasheet, P87C58X2BBD,157 pinout, P87C58X2BBD,157 application, or P87C58X2BBD,157 equivalent, key selection criteria include OTP memory size (32 KB), LQFP44 package compatibility, 6-/12-clock software-selectable timing, power-down wake-up via INT0/INT1, and UART auto-address recognition for multi-drop bus systems.
Technical Context
This device implements a static CMOS 80C51 core with enhanced peripherals including Timer 2 (capture/compare), programmable clock-out on P1.0, and dual data pointers. Its CKCON register controls 6-/12-clock operation, enabling runtime switching between 30 MHz (6-clk @ 5 V) and 33 MHz (12-clk @ 5 V) maximum frequencies.
The microcontroller supports low-power operation with idle mode (CPU halted, peripherals active) and power-down mode (oscillator stopped, RAM retained down to 2.0 V). Wake-up from power-down is enabled via level-sensitive external interrupts on INT0 or INT1, controlled by WUPD bit in AUXR1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 80C51-compatible static CMOS CPU with Boolean processor and dual data pointers - enables legacy 8051 code portability and efficient pointer arithmetic for buffer management. |
| Memory | 32 KB on-chip OTP ROM + 256 B RAM - sufficient for standalone embedded applications without external code storage; OTP prevents field reprogramming but ensures firmware integrity. |
| Operating Voltage | 2.7 V to 5.5 V - supports battery-backed (3 V) and industrial rail (5 V) operation; LPEP bit reduces current below 4 V by disabling EPROM analog circuitry. |
| Max Clock Frequency | 30 MHz (6-clock mode) / 33 MHz (12-clock mode) at 5 V - delivers higher instruction throughput than standard 8051 while maintaining cycle-accurate timing for legacy peripherals. |
| Timers & Counters | Three 16-bit timers: T0/T1 (standard 80C51) + T2 (enhanced capture/compare) - supports PWM generation, input capture, baud-rate generation, and clock-out on P1.0 simultaneously. |
| Serial Interface | Full-duplex UART with framing error detection and automatic address recognition - enables reliable multi-processor communication on shared RS-485 buses without software address filtering overhead. |
| Power Modes | Idle (CPU halted, RAM/timers/UART active) and Power-Down (oscillator stopped, RAM retained) - allows microsecond wake-up latency and sub-μA standby current in battery-critical designs. |
Pinout & Package
LQFP44 package (SOT389-1), 10 mm × 10 mm × 1.4 mm body, 0 °C to +70 °C operating range.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0–P0.7 | Open-drain bidirectional I/O / AD0–AD7 / A0–A7 | Multiplexed address/data bus for external memory access; requires external pull-ups during program verification or when used as high-impedance inputs. |
| P1.0/T2 | General I/O / Timer 2 external count input / Clock-out | Configurable as timer input or 50% duty-cycle clock output (61 Hz–4 MHz at 16 MHz osc); selected via T2CON.C/T2 and T2MOD.T2OE bits. |
| P1.1/T2EX | General I/O / Timer 2 reload/capture/direction control | Enables edge-triggered reload or capture of T2 counter value; supports quadrature decoding and pulse-width measurement. |
| P2.0–P2.7 | Bidirectional I/O / A8–A15 | Provides high-order address byte during 16-bit external memory accesses; emits P2 SFR contents during 8-bit MOVX @Ri operations. |
| P3.0/RxD | Serial input | Asynchronous UART receive pin; supports framing error detection and automatic address recognition in multi-processor mode. |
| P3.1/TxD | Serial output | Asynchronous UART transmit pin; outputs serial data with programmable stop bits and parity via SCON register. |
| P3.2/INT0 | External interrupt 0 input | Level-sensitive wake-up source from Power-Down mode; must be held low until oscillator stabilizes post-wake. |
| P3.6/WR & P3.7/RD | External memory strobes | Active-low write/read enable signals for external data memory interfacing; synchronized with ALE for timing-critical bus cycles. |
| XTAL1/XTAL2 | Oscillator input/output | Supports crystal (1–24 MHz), ceramic resonator, or external clock drive; internal inverter enables self-contained timing without external components. |
| EA/VPP | External access enable / Programming voltage | When high, executes from internal OTP up to 0x7FFF; when low, fetches code from external memory; receives 12.75 V during OTP programming. |
| RST | Reset input | Active-high reset requiring ≥2 machine cycles (24/12 osc periods in 12-/6-clock mode); internal pull-down enables power-on reset with RC network. |
| ALE/PROG | Address latch enable / Programming pulse | Outputs 1/6 (12-clk) or 1/3 (6-clk) oscillator frequency for external latch timing; disabled via AUXR.0 to reduce EMI during non-memory cycles. |
Key Features
| Feature | Design Value |
|---|---|
| 6-/12-clock software-selectable mode | CKCON.X2 bit enables runtime switching between 6- and 12-clock operation - doubles instruction throughput without changing hardware or oscillator. |
| Programmable clock-out on P1.0 | Generates precise 50% duty-cycle clocks (61 Hz–4 MHz @ 16 MHz osc) using Timer 2 - eliminates need for external clock generators in sensor sync or test signal applications. |
| Three-level interrupt priority with six sources | Four priority levels (IP register) and six interrupt vectors (INT0/INT1/T0/T1/RI/TI) - enables deterministic response to time-critical events like motor commutation or safety shutdown. |
| Low-EMI design features | Configurable ALE inhibit, slew-rate-controlled outputs, and 6-clock mode reduce radiated emissions - simplifies EMC compliance in industrial environments. |
| OTP security bits and encryption array | Three OTP security bits and 64-byte encryption array prevent unauthorized firmware readout - protects proprietary control algorithms in OEM equipment. |
Applications
| Industrial PLC I/O Module | Legacy Equipment Controller |
|---|---|
|
Use Scenario: Standalone I/O expansion module in DIN-rail mounted PLCs, managing 16 digital inputs and 8 relay outputs via discrete logic and optocouplers. IC Role / Device Role / Timing Role: Central controller executing ladder logic scan, handling UART-based Modbus RTU communication, and generating precise timing for output pulse-width modulation. Use Value: 32 KB OTP accommodates full Modbus stack + application logic; T2 capture/compare enables accurate 100 μs-resolution input timestamping for motion control feedback. |
Use Scenario: Retrofit controller for aging CNC machine tools, replacing obsolete 8051 variants while retaining identical pinout and firmware structure. IC Role / Device Role / Timing Role: Drop-in replacement MCU with identical 80C51 instruction set, supporting existing assembly code and external memory interface without PCB modification. Use Value: LQFP44 package matches footprint of legacy DIP40 via adapter; 6-clock mode restores original 12 MHz timing behavior on 24 MHz crystal. |
| Smart Energy Meter Interface | RS-485 Multi-Drop Sensor Hub |
|
Use Scenario: Communication interface unit in polyphase energy meters, aggregating metrology IC data and transmitting via isolated RS-485 to concentrators. IC Role / Device Role / Timing Role: UART master coordinating SPI reads from ADCs and framing Modbus ASCII packets with CRC-16 checksums. Use Value: Full-duplex UART with auto-address recognition eliminates polling overhead; 256 B RAM buffers multiple meter registers for burst transmission during RF wake-up windows. |
Use Scenario: Central node in building automation system collecting temperature/humidity readings from 12 remote sensors over half-duplex RS-485. IC Role / Device Role / Timing Role: Multi-processor UART controller assigning unique addresses to each sensor and managing collision-free polling sequence. Use Value: Framing error detection identifies noisy bus segments; programmable clock-out synchronizes sensor sampling across nodes using shared 1 MHz reference. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT89C55WD-24PU | 20 KB Flash (not OTP), 24 MHz max, DIP40 only, no T2 or clock-out | Lacks Timer 2 and programmable clock-out; limited to 20 KB code space and through-hole assembly | Select when field firmware updates are required and LQFP44 footprint is not mandatory. |
| P89C664FA | 64 KB Flash, 40 MHz, 1024 B RAM, ISP-capable, includes PCA and I²C | Higher integration with peripheral-rich feature set; incompatible OTP-to-Flash migration path | Select when future scalability to larger code base or added peripherals (PCA, I²C) is anticipated. |
Compared with AT89C55WD-24PU and P89C664FA, the P87C58X2BBD,157 offers deterministic OTP-based firmware security and exact 80C51 timing compatibility - critical for safety-certified industrial controllers where flash wear-out or ISP vulnerability is unacceptable.
Availability
P87C58X2BBD,157 is available at Aetrix Electronics and suitable for industrial PLC modules, legacy equipment retrofits, smart energy meter interfaces, and RS-485 sensor hubs requiring stable component supply and long-term obsolescence support.
Supply support for P87C58X2BBD,157 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Philips Semiconductors (now NXP Semiconductors) is a pioneer in integrated circuits, delivering high-reliability, industry-standard microcontrollers since the 1980s.
The P87C5xX2 family was designed for cost-sensitive, high-volume industrial control applications requiring proven 80C51 compatibility, OTP firmware security, and robust operation across extended temperature ranges.
FAQ
What is the maximum operating frequency of the P87C58X2BBD,157 and under what conditions?
The P87C58X2BBD,157 supports up to 33 MHz in 12-clock mode and 30 MHz in 6-clock mode - both at VCC = 5 V ± 10%. At lower voltages (2.7–5.5 V), the maximum frequency is limited to 16 MHz regardless of clock mode. The actual frequency depends on oscillator stability, load capacitance, and PCB layout; external crystal values between 1 MHz and 24 MHz are supported per the datasheet.
Does the P87C58X2BBD,157 support in-system programming or field firmware updates?
No, the P87C58X2BBD,157 uses one-time-programmable (OTP) ROM, which cannot be erased or rewritten after initial programming. Firmware must be verified and finalized before OTP programming using a parallel programmer. This ensures immutability and security but precludes field updates - making it suitable for safety-critical or tamper-resistant applications where code integrity is paramount.
How does the P87C58X2BBD,157 handle power-down wake-up, and what pins are supported?
The P87C58X2BBD,157 exits power-down mode via hardware reset or level-sensitive external interrupts on INT0 (P3.2) or INT1 (P3.3). The WUPD bit in AUXR1 must be set to enable interrupt wake-up. After wake-up, the oscillator restarts and stabilizes (typically <10 ms), and execution resumes from the instruction following the power-down command - with RAM and SFRs fully preserved.
What is the function of the T2EX pin (P1.1) on the P87C58X2BBD,157 and how is it configured?
On the P87C58X2BBD,157, P1.1 serves as T2EX - Timer 2's external reload/capture/counter direction control input. When T2CON.EXEN2 = 1, a 1→0 transition on T2EX triggers reload of RCAP2H/L into TL2/TH2; when C/T2 = 1, it toggles counting direction for up/down counter operation. Configuration is done exclusively via SFR writes - no external pull-up is required as internal weak pull-ups apply.
Can the P87C58X2BBD,157 operate reliably at 3.3 V, and what performance trade-offs apply?
Yes, the P87C58X2BBD,157 is fully specified for operation from 2.7 V to 5.5 V. At 3.3 V, maximum clock frequency is 16 MHz in either 6- or 12-clock mode. The LPEP bit (AUXR.4) should be set to disable EPROM analog circuitry, reducing supply current by ~2 mA - improving battery life in portable instrumentation without affecting core functionality or OTP read reliability.
P87C58X2BBD,157 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 44-LQFP
- Series:
- 87C
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 33MHz
- Connectivity:
- EBI/EMI, UART/USART
- Peripherals:
- POR
- Number of I/O:
- 32
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P87C58X2BBD,157 FAQ
1.How can I place an order for P87C58X2BBD,157 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87C58X2BBD,157 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of P87C58X2BBD,157 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87C58X2BBD,157 is usually 5 days.
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For technical support, including P87C58X2BBD,157 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87C58X2BBD,157 requirements.
6.How does Aetrix verify that P87C58X2BBD,157 is sourced from the original manufacturer or authorized distributors?
All P87C58X2BBD,157 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87C58X2BBD,157 meets industry standards.
7.What is the process for return or replacement of P87C58X2BBD,157?
All P87C58X2BBD,157 units undergo pre-shipment inspection (PSI). If there is an issue with P87C58X2BBD,157, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87C58X2BBD,157 part is unused and in its original packaging.
Return procedure for P87C58X2BBD,157:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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