NXP Semiconductors P87LPC768FN,112
- Part No.:
- P87LPC768FN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
P87LPC768FN,112.pdf
- Description:
- IC MCU 8BIT 4KB OTP 20DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P87LPC768FN,112 from NXP Semiconductors (formerly Philips) is a 20-pin, OTP-based 8-bit microcontroller built on an accelerated 80C51 core, delivering 300–600 ns instruction cycles at 20 MHz. It integrates a 4-channel 8-bit ADC, four independent PWM outputs, two analog comparators, I²C and UART interfaces, and operates from 2.7 V to 6.0 V - enabling compact, low-power sensor interface and motor control in industrial and appliance applications.
For engineers reviewing the P87LPC768FN,112 datasheet, P87LPC768FN,112 pinout, P87LPC768FN,112 application, or P87LPC768FN,112 equivalent, key selection considerations include its 4 kB OTP code memory, 128-byte RAM, programmable port configurations (quasi-bidirectional/open-drain/push-pull), integrated watchdog with on-chip oscillator, and support for Power Down mode with 1 µA typical current.
Technical Context
The P87LPC768FN,112 implements an enhanced 80C51 CPU executing instructions in 6 or 12 clock cycles - twice the speed of standard 80C51 parts - with optional standard timing via CLKR configuration. Its analog subsystem includes a ratiometric 8-bit successive-approximation ADC with 9.3 µs conversion time at 20 MHz and dual analog comparators with configurable reference inputs.
Digital I/O flexibility is achieved through per-pin programmable output modes (including LED drive up to 20 mA), selectable Schmitt-trigger inputs, and slew-rate-controlled outputs (~10 ns ramp time). The device supports full-duplex UART, I²C master/slave operation, and eight keypad interrupt inputs - all managed under four-level interrupt priority with dedicated SFRs for PWM shadow/compare registers and A/D control (ADCON).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Accelerated 80C51 architecture; executes most instructions in 6 clocks - enables 20 MHz operation with 300 ns min. cycle time. |
| Memory | 4 kB on-chip OTP EPROM code memory + 128-byte RAM + 32-byte customer code space for serialization or calibration data. |
| A/D Converter | Four-channel, 8-bit multiplexed ADC; 9.3 µs conversion time at fosc = 20 MHz; ratiometric operation referenced to VDD/VSS. |
| PWM Outputs | Four independent PWM channels (PWM0–PWM3); each with dedicated compare shadow registers (CPSW0–CPSW3) and configurable resolution/timing. |
| Operating Voltage | 2.7 V to 6.0 V digital supply range; supports direct battery-powered operation (e.g., 3 V Li-ion or 5 V rail) without level-shifting. |
| Power Modes | Idle and Power Down modes; typical Power Down current is 1 µA - suitable for wake-on-interrupt sensor nodes with long battery life. |
| Package | 20-pin plastic DIP (SOT146–1); compatible with through-hole prototyping and legacy industrial PCB layouts. |
Pinout & Package
20-pin plastic Dual In-Line Package (DIP), SOT146–1 footprint. Through-hole mounting with 0.3-inch row spacing; RoHS-compliant lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (P0.0) | CMP2 / PWM3 | Comparator 2 output or Pulse Width Modulator 3 output - shared function selected via SFR configuration. |
| 2 (P1.7) | PWM2 | Dedicated PWM channel 2 output; supports variable-duty-cycle generation for DC motor control or dimming. |
| 3 (P1.6) | PWM1 | Dedicated PWM channel 1 output; independently controllable with CPSW1 shadow register. |
| 4 (P1.5) | RST | Active-low reset input; configurable as Schmitt-trigger input when not used for reset - eliminates external RC network if on-chip POR enabled. |
| 5 (VSS) | Ground | 0 V reference for analog and digital circuits; must be low-impedance connection to minimize noise coupling into ADC/comparators. |
| 6 (X1) | Oscillator Input | Crystal/resonator or external clock input; internal oscillator circuit supports 20 MHz crystal or RC option (no external components required). |
| 7 (X2/CLKOUT) | Oscillator Output / Clock Out | Crystal drive output or divided-by-6 CPU clock output - enables trace clock monitoring or synchronous peripheral timing. |
| 8 (INT1) | External Interrupt 1 | Edge-triggered interrupt input; supports fast event capture (e.g., encoder pulse or safety interlock signal). |
| 9 (SDA/INT0) | I²C Data / Interrupt 0 | Open-drain bidirectional I²C bus line or external interrupt source - requires external pull-up; dual-function reduces pin count in space-constrained designs. |
| 10 (SCL/T0) | I²C Clock / Timer 0 Input | Open-drain I²C clock line or timer/counter 0 external count input - supports synchronized sensor communication or pulse counting. |
| 11 (P0.1) | CIN2B / PWM0 | Comparator 2 positive input B or PWM0 output - pin function selected by peripheral enable bits in SFRs. |
| 12 (P0.2) | CIN2A / BRAKE | Comparator 2 positive input A or PWM brake control input - enables hardware emergency stop for motor drivers. |
| 13 (P0.3) | CIN1B / AD0 | Comparator 1 positive input B or ADC channel 0 input - shared analog input simplifies multi-sensor front-end design. |
| 14 (P0.4) | CIN1A / AD1 | Comparator 1 positive input A or ADC channel 1 input - allows simultaneous comparator thresholding and ADC sampling on same pin group. |
| 15 (VDD) | Power Supply | Primary power rail for digital and analog blocks; supplies ADC reference and internal regulators - decoupling capacitor required near pin. |
| 16 (P0.6) | CMP1 / AD3 | Comparator 1 output or ADC channel 3 input - supports closed-loop analog control with direct feedback path. |
| 17 (P1.0) | TxD | UART transmit output; CMOS-level serial output for debug logging or host communication without level shifters. |
| 18 (P0.7) | T1 | Timer 1 external count input or overflow output - enables high-resolution event timing or gated PWM generation. |
| 19 (P1.1) | RxD | UART receive input; Schmitt-triggered for noise immunity on asynchronous serial links. |
| 20 (P0.0) | PWM3 / CMP2 | Repeats Pin 1 function - confirms dual-role assignment across port mapping; no functional duplication. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Port Output Modes | Per-pin selection of quasi-bidirectional, open-drain, push-pull, or input-only - enables direct LED driving (20 mA), I²C compliance, and clean digital interfacing without external buffers. |
| On-Chip Watchdog with Independent Oscillator | Separate RC oscillator eliminates dependency on main clock; eight selectable timeout values allow precise system recovery tuning without external components. |
| Configurable Analog Input Handling | PT0AD register disables digital inputs on Port 0 pins used for ADC/comparators - prevents sampling errors caused by digital switching noise on analog nodes. |
| Low-Voltage Reset (LVR) | Two preset brownout thresholds (e.g., 2.5 V or 3.8 V) - enables graceful shutdown or fault logging before supply collapse in battery-operated systems. |
| Controlled Slew Rate Outputs | ~10 ns minimum ramp time on all port outputs - reduces EMI emissions and prevents signal integrity issues in mixed-signal PCB layouts. |
Applications
| Industrial Sensor Node | Appliance Motor Control |
|---|---|
Use Scenario: Standalone temperature/humidity monitor with local display and wireless uplink. IC Role / Device Role / Timing Role: Central controller managing ADC sampling, PWM-driven backlight, UART debug interface, and I²C sensor reads. Use Value: Integrated 4-channel ADC and four PWMs eliminate external signal conditioning ICs; 1 µA Power Down current extends battery life to >2 years on coin cell. | Use Scenario: Fan speed regulation in HVAC system with thermal protection and user interface. IC Role / Device Role / Timing Role: Real-time motor driver using PWM0–PWM3 for multi-phase control, comparator-based overtemperature detection, and UART for service diagnostics. Use Value: Hardware brake (BRAKE pin) and comparator outputs enable immediate motor shutdown on fault - meets IEC 60335 safety requirements without external logic. |
| Smart Power Outlet | LED Lighting Dimmer |
Use Scenario: Energy-monitoring outlet with relay control, current sensing, and Bluetooth module interface. IC Role / Device Role / Timing Role: System manager handling ADC-based current measurement, zero-cross detection via INT0, and I²C communication with BLE SoC. Use Value: Keypad interrupt (KBI) inputs repurposed for button debouncing; 32-byte customer EPROM stores unique MAC address and calibration offsets. | Use Scenario: Triac-dimmable LED driver with smooth brightness control and thermal foldback. IC Role / Device Role / Timing Role: PWM generator synchronizing phase-cut dimming signals with AC line via T0 input, while ADC monitors heatsink temperature. Use Value: Dedicated PWM channels (PWM1/PWM2) drive separate warm/cool LED strings; comparator reference (CMPREF) provides stable thermal trip point independent of VDD variation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC922FA,112 | Enhanced 80C51 core with 8 kB flash, 512-byte RAM, and higher ADC resolution (10-bit); operates up to 18 MHz at 3 V. | Requires flash programming infrastructure; better suited for field-upgradable firmware but lacks OTP security for IP protection. | Select when firmware updates are needed; avoid if one-time programming and anti-tampering are critical. |
| AT89LP2052-20PU | 8051-compatible with 2 kB flash, 128-byte RAM, no integrated ADC or comparators; requires external analog front-end. | Lower BOM cost for purely digital control tasks; unsuitable for direct sensor interfacing without added components. | Choose only for simple logic replacement where analog integration is handled externally. |
Compared with P87LPC768FN,112, the P89LPC922FA,112 offers greater memory and ADC precision but sacrifices OTP security and increases toolchain complexity, while the AT89LP2052-20PU reduces cost only when analog functions are implemented separately - making P87LPC768FN,112 optimal for integrated, cost-sensitive embedded sensing.
Availability
P87LPC768FN,112 is available at Aetrix Electronics and suitable for industrial sensor nodes, appliance motor controllers, smart power outlets, and LED lighting dimmers requiring stable component supply across extended temperature ranges (–45 °C to +85 °C).
Supply support for P87LPC768FN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with roots in Philips' pioneering microcontroller development.
The P87LPC768FN,112 belongs to NXP's legacy LPC700 family - designed specifically for cost-sensitive, low-pin-count embedded control where analog integration, ultra-low power, and robustness in harsh environments are essential.
FAQ
What is the maximum operating frequency of the P87LPC768FN,112 and under what voltage conditions?
The P87LPC768FN,112 operates up to 20 MHz when VDD is between 4.5 V and 6.0 V, and up to 10 MHz when VDD is between 2.7 V and 6.0 V. This dual-speed specification allows flexible power supply design - supporting both 5 V legacy rails and 3 V battery operation without performance penalty below 10 MHz. The P87LPC768FN,112 achieves this via its configurable oscillator and accelerated 80C51 core.
Does the P87LPC768FN,112 support in-system programming (ISP) or is it OTP-only?
The P87LPC768FN,112 uses 4 kB of one-time-programmable (OTP) EPROM for code storage and does not support in-system programming. Programming is performed via parallel EPROM programmer using the VPP pin (not exposed in DIP package) during manufacturing. The P87LPC768FN,112 includes two EPROM security bits to prevent unauthorized readout of application code - ensuring firmware IP protection in production units.
How many analog input channels does the P87LPC768FN,112 ADC support, and which pins are used?
The P87LPC768FN,112 features a four-channel 8-bit multiplexed ADC using Port 0 pins P0.3 (AD0), P0.4 (AD1), P0.5 (AD2), and P0.6 (AD3) as analog inputs. These share pins with comparator inputs and general-purpose I/O, requiring software configuration of PT0AD and port mode registers to disable digital functions before sampling - ensuring accurate conversion without noise coupling.
Can the P87LPC768FN,112 generate complementary PWM outputs with dead-time control?
The P87LPC768FN,112 does not include hardware dead-time insertion or complementary PWM pair generation. It provides four independent PWM outputs (PWM0–PWM3) with individual duty-cycle control via CPSW shadow registers, but timing coordination and dead-time insertion must be implemented in firmware using timer interrupts or GPIO toggling. The BRAKE input (P0.2) supports hardware emergency stop but does not configure automatic complementary output behavior in the P87LPC768FN,112.
What are the temperature grade and packaging details for the P87LPC768FN,112?
The P87LPC768FN,112 is specified for industrial temperature operation from –45 °C to +85 °C and is supplied in a 20-pin plastic Dual In-Line Package (DIP) with SOT146–1 mechanical outline. This through-hole package supports manual assembly, socket-based testing, and legacy board designs - distinguishing it from the SO-package variants (e.g., P87LPC768FD) intended for surface-mount production.
P87LPC768FN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Series:
- LPC700
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 20MHz
- Connectivity:
- I2C, UART/USART
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 18
- Program Memory Size:
- 4KB (4K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 128 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 6V
- Data Converters:
- A/D 4x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P87LPC768FN,112 FAQ
1.How can I place an order for P87LPC768FN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P87LPC768FN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P87LPC768FN,112 reliable?
The price and inventory of P87LPC768FN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P87LPC768FN,112 is usually 5 days.
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5.How can I obtain technical support or documentation for P87LPC768FN,112?
For technical support, including P87LPC768FN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P87LPC768FN,112 requirements.
6.How does Aetrix verify that P87LPC768FN,112 is sourced from the original manufacturer or authorized distributors?
All P87LPC768FN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P87LPC768FN,112 meets industry standards.
7.What is the process for return or replacement of P87LPC768FN,112?
All P87LPC768FN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P87LPC768FN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P87LPC768FN,112 part is unused and in its original packaging.
Return procedure for P87LPC768FN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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