NXP Semiconductors P89LPC9107FDH,129
- Part No.:
- P89LPC9107FDH,129
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC9107FDH,129.pdf
- Description:
- IC MCU 8BIT 1KB FLASH 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P89LPC9107FDH,129 from NXP Semiconductors is a low-cost, 14-pin TSSOP 8-bit microcontroller based on an accelerated two-clock 80C51 core, delivering up to 6× performance vs. standard 8051. It integrates 1 kB byte-erasable flash, 128-byte RAM, dual 16-bit timers, 4-channel 8-bit ADC, DAC output, analog comparator, enhanced UART with fractional baud rate generator, and 23-bit RTC/system timer - enabling compact sensor interface and control applications in industrial and consumer systems.
For engineers reviewing the P89LPC9107FDH,129 datasheet, P89LPC9107FDH,129 pinout, P89LPC9107FDH,129 application, or P89LPC9107FDH,129 equivalent, this page delivers verified technical context, package-specific pin functions, real-world use cases, and validated alternative options for embedded design and sourcing decisions.
Technical Context
The P89LPC9107FDH,129 implements a two-clock-accelerated 80C51 CPU architecture executing instructions in 2–4 clocks, achieving 136–272 ns instruction cycles at 7.3728 MHz (RC oscillator, clock-doubling mode). Its integrated peripherals include a programmable 23-bit system timer usable as RTC, four multiplexed ADC inputs with selectable reference, and a single DAC output - all sharing Port 0 pins with keypad interrupt and comparator functionality.
It supports four interrupt priority levels, in-application programming (IAP-Lite), and configurable port output modes (quasi-bidirectional, open-drain, push-pull). The device features a factory-calibrated ±1 % internal RC oscillator, 2.4–3.6 V operation with 5 V-tolerant I/O, and ultra-low-power Power-down mode (<1 µA typical) with wake-up via LOW interrupt input.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Accelerated two-clock 80C51 - executes all instructions in 2–4 clocks, enabling 6× throughput vs. legacy 8051 at same frequency. |
| Flash Memory | 1 kB byte-erasable flash organized in 256-byte sectors and 16-byte pages - supports non-volatile data storage via single-byte erase. |
| RAM | 128-byte on-chip RAM - sufficient for small real-time control stacks and sensor data buffering without external memory. |
| ADC/DAC | Four-input 8-bit ADC + single DAC output on shared Port 0 pins - enables analog sensing and simple actuator control in space-constrained designs. |
| Timers & RTC | Dual 16-bit timers + 23-bit system timer - provides flexible timing, PWM generation, and real-time clock functionality with no external components required. |
| UART | Enhanced UART with fractional baud rate generator, break detection, framing error detection, and automatic address detection - ensures robust serial communication across variable bus speeds. |
| Operating Voltage | 2.4 V to 3.6 V supply with 5 V-tolerant I/O pins - allows direct interfacing with 5 V logic and mixed-voltage systems without level shifters. |
| Package | TSSOP14 (SOT402-1), 4.4 mm body width - surface-mount package optimized for high-density PCB layouts and automated assembly. |
Pinout & Package
Package: Plastic thin shrink small outline package; 14 leads; body width 4.4 mm (SOT402-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.1/KBI1/AD10 | Port 0 bit 1 / Keypad input 1 / ADC channel 0 | Configurable I/O supporting keyboard scan, analog sensing, or general-purpose digital I/O with Schmitt trigger input. |
| P0.2/KBI2/AD11 | Port 0 bit 2 / Keypad input 2 / ADC channel 1 | Shared function pin enabling simultaneous keypad event detection and analog voltage measurement. |
| P0.3/CIN1B/AD12 | Port 0 bit 3 / Comparator 1 positive input / ADC channel 2 | Supports analog comparison against reference (CMPREF) or conversion of external signal to 8-bit digital value. |
| P0.4/CIN1A/AD13/DAC1 | Port 0 bit 4 / Comparator 1 negative input / ADC channel 3 / DAC output | Multi-function pin capable of comparator input, ADC input, or generating analog output (0–VDD range) for simple control signals. |
| P0.5/CMPREF/CLKIN | Port 0 bit 5 / Comparator reference / External clock input | Provides precision reference for analog comparator or accepts external timing source for synchronous operation. |
| P0.7/T1/CLKOUT | Port 0 bit 7 / Timer 1 overflow/PWM / Clock output | Delivers timer-based PWM waveform or buffered system clock signal for trace/debug or peripheral synchronization. |
| P1.0/TXD | Port 1 bit 0 / UART transmit data | Drives serial TX line with programmable slew rate to reduce EMI; supports standard and custom baud rates via fractional generator. |
| P1.1/RXD | Port 1 bit 1 / UART receive data | Accepts serial RX data with framing error detection and automatic address recognition for multi-drop bus systems. |
| P1.2/T0 | Port 1 bit 2 / Timer 0 overflow/PWM | Generates precise PWM outputs or captures external events with 16-bit resolution for motor or LED control. |
| P1.5/RST | Port 1 bit 5 / Reset input (input-only) | Active-LOW reset pin requiring external pull-up; enables hardware reset initiation and brownout detection when configured. |
| VDD | Power supply | Primary 2.4–3.6 V supply rail; powers core, peripherals, and I/O; supports ultra-low-power Power-down mode. |
| VSS | Ground | 0 V reference for analog and digital circuits; must be low-impedance connection for stable ADC and oscillator operation. |
| n.c. | No connect | Two unconnected pins (pins 11 and 13 in TSSOP14 layout) - must remain floating per datasheet; no routing or soldering required. |
Key Features
| Feature | Design Value |
|---|---|
| Byte-erasable flash memory | Enables firmware updates and non-volatile parameter storage without full chip erase - critical for field-programmable devices and calibration data retention. |
| Factory-calibrated ±1 % RC oscillator | Eliminates need for external crystal or resonator, reducing BOM cost and board area while maintaining timing accuracy for UART and RTC functions. |
| Configurable port output modes | Per-pin selection of quasi-bidirectional, open-drain, or push-pull drive - simplifies interface to diverse loads (LEDs, switches, sensors) without external buffers. |
| Ultra-low-power Power-down mode | Typical current <1 µA with voltage comparators disabled - extends battery life in portable and energy-harvesting applications. |
| Port input pattern match detection | Triggers interrupt when Port 0 pins match or mismatch user-defined bit pattern - enables efficient keypad scanning and state-change monitoring. |
| LED drive capability (20 mA per pin) | Direct driving of status LEDs or small indicators without external transistors - reduces component count in HMI and diagnostic subsystems. |
Applications
| Industrial Sensor Node | Smart Home Controller |
|---|---|
Use Scenario: Compact environmental monitor measuring temperature, humidity, and light using analog sensors and reporting via UART to gateway. IC Role / Device Role / Timing Role: Central MCU managing ADC sampling, RTC-stamped data logging, UART transmission, and low-power sleep/wake cycles. Use Value: Integrated ADC, DAC, RTC, and 5 V-tolerant I/O eliminate six discrete components, reducing PCB area by >30 % and enabling sub-1 cm² node design. | Use Scenario: Wall-mounted HVAC controller with keypad input, LED feedback, and serial communication to thermostat network. IC Role / Device Role / Timing Role: Real-time control unit handling keypad scan, LED drive, analog sensor reading, and UART protocol stack. Use Value: Keypad interrupt + pattern match detection cuts polling overhead by 90 %; 20 mA LED drive supports bright visual indicators without external drivers. |
| Portable Medical Device | Energy-Efficient Metering Module |
Use Scenario: Battery-powered pulse oximeter acquiring analog photodiode signals and computing SpO₂ values locally before wireless upload. IC Role / Device Role / Timing Role: Signal acquisition MCU performing synchronized ADC sampling, digital filtering, and low-power idle management between measurements. Use Value: Dual 16-bit timers enable precise LED pulse timing and ADC sampling windows; <1 µA Power-down current extends battery life to >12 months. | Use Scenario: DIN-rail mounted electricity meter front-end capturing voltage/current waveforms and calculating RMS values. IC Role / Device Role / Timing Role: Analog acquisition engine with 8-bit ADC, comparator for overvoltage detection, and UART for configuration and data export. Use Value: On-chip comparator with selectable reference provides fast overvoltage trip (<1 µs response); 2.4–3.6 V operation ensures compatibility with isolated DC-DC supplies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC9107FN | DIP14 package (SOT27-1), identical electrical specs and pinout mapping except for physical form factor and thermal characteristics. | Suitable for prototyping, through-hole assembly, or legacy board upgrades where TSSOP rework is impractical. | Select P89LPC9107FN for hand-soldered development or compatibility with existing DIP footprints; P89LPC9107FDH,129 is preferred for volume SMT production. |
| P89LPC9103FTK | HVSON10 package (SOT650-1), lacks T0/T1 PWM outputs and CLKOUT; retains UART, ADC, and RTC but with only 8 I/O pins. | Better suited for ultra-compact, UART-centric applications like sensor transmitters where PWM and clock output are unnecessary. | Choose P89LPC9103FTK when board space is critical and PWM/CLKOUT are unused; P89LPC9107FDH,129 provides full peripheral set in TSSOP14. |
Compared with P89LPC9107FN, the P89LPC9107FDH,129 offers superior thermal performance and smaller footprint for automated assembly; versus P89LPC9103FTK, it adds two PWM-capable timers and clock output - enabling closed-loop control and system-level timing distribution not possible in the 10-pin variant.
Availability
P89LPC9107FDH,129 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home controllers, portable medical devices, and energy-efficient metering modules requiring stable component supply, long-term lifecycle support, and consistent parametric performance.
Supply support for P89LPC9107FDH,129 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC9107FDH,129 belongs to NXP's LPC900 family of low-pin-count, cost-optimized 8-bit MCUs designed for space-constrained embedded control tasks where integration, power efficiency, and ease of deployment outweigh raw processing power.
FAQ
What is the maximum operating frequency of the P89LPC9107FDH,129?
The P89LPC9107FDH,129 operates with a factory-calibrated internal RC oscillator at 7.3728 MHz, optionally doubled to 14.7456 MHz via clock-doubling mode. When using an external 18 MHz clock, instruction cycle times improve to 111–222 ns. The device does not support frequencies above 18 MHz, and oscillator configuration is controlled via UCFG registers.
Does the P89LPC9107FDH,129 support in-system programming (ISP)?
Yes, the P89LPC9107FDH,129 supports In-Application Programming (IAP-Lite) and serial flash ICP via UART, allowing firmware updates without removing the device from the board. Flash security bits prevent unauthorized readout of code memory, and byte-erase capability enables safe storage of calibration data alongside application code.
How many I/O pins are available on the P89LPC9107FDH,129 in standard configuration?
The P89LPC9107FDH,129 provides up to 10 I/O pins when using internal oscillator and reset options: P0.1, P0.2, P0.3, P0.4, P0.5, P0.7, P1.0, P1.1, P1.2, and P1.5. Pin P1.5 is input-only (RST), and two pins (11 and 13) are no-connect in the TSSOP14 package, leaving 10 functional I/Os.
Can the P89LPC9107FDH,129 generate PWM signals?
Yes, the P89LPC9107FDH,129 supports PWM generation on both Timer 0 (T0) and Timer 1 (T1) outputs - accessible via P1.2 and P0.7 respectively. These pins can be configured as overflow/PWM outputs in TMOD register, enabling variable-duty-cycle waveforms for LED dimming, motor control, or analog signal synthesis.
What is the purpose of the CLKOUT pin on the P89LPC9107FDH,129?
The CLKOUT pin (P0.7) on the P89LPC9107FDH,129 provides a buffered output of the internal CPU clock or divided system clock, useful for debugging, synchronizing external logic, or feeding clock signals to companion ICs. Its operation is enabled via the DIVM register and requires proper configuration of the oscillator divider and port mode settings.
P89LPC9107FDH,129 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- UART/USART
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 12
- Program Memory Size:
- 1KB (1K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 4x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC9107FDH,129 FAQ
1.How can I place an order for P89LPC9107FDH,129 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC9107FDH,129 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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For technical support, including P89LPC9107FDH,129 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC9107FDH,129 requirements.
6.How does Aetrix verify that P89LPC9107FDH,129 is sourced from the original manufacturer or authorized distributors?
All P89LPC9107FDH,129 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC9107FDH,129 meets industry standards.
7.What is the process for return or replacement of P89LPC9107FDH,129?
All P89LPC9107FDH,129 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC9107FDH,129, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC9107FDH,129 part is unused and in its original packaging.
Return procedure for P89LPC9107FDH,129:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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