NXP Semiconductors P89LPC912FDH,129
- Part No.:
- P89LPC912FDH,129
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC912FDH,129.pdf
- Description:
- IC MCU 8BIT 1KB FLASH 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P89LPC912FDH,129 from NXP Semiconductors is an 8-bit microcontroller based on a two-clock 80C51 core, delivering six times the instruction throughput of standard 80C51 devices at 18 MHz. It integrates 1 kB flash code memory (byte-erasable), 128 B RAM, two 16-bit timers, a 23-bit system timer/RTC, and dual analog comparators - all in a 14-pin TSSOP package. It targets low-cost embedded control applications such as sensor interfaces and small appliance controllers where board space and component count are critical.
For engineers reviewing the P89LPC912FDH,129 datasheet, P89LPC912FDH,129 pinout, P89LPC912FDH,129 application, or P89LPC912FDH,129 equivalent, this device offers verified support for internal RC oscillator operation (±1 % calibration), 2.4–3.6 V supply with 5 V-tolerant I/O, and in-application programming (IAP-Lite) enabling non-volatile data storage in flash - key selection criteria for cost-sensitive, low-power industrial and consumer designs.
Technical Context
The P89LPC912FDH,129 implements a high-performance accelerated 2-clock 80C51 CPU executing instructions in two to four clocks, achieving 111–222 ns instruction cycles at 18 MHz. Its architecture includes dedicated hardware for keypad interrupt pattern matching on Port 0, configurable slew-rate-controlled outputs (≈10 ns ramp time), and a separate on-chip watchdog oscillator for fail-safe reset generation.
It supports multiple clock sources: external crystal/resonator (XTAL1/XTAL2), internal RC oscillator (factory-calibrated to ±1 %), or external clock input. The system timer operates as both RTC and general-purpose 23-bit counter, while dual analog comparators provide selectable reference and inputs (CIN1A/CIN2A, CMPREF, CMP1 output) without requiring external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Two-clock 80C51 CPU - executes all instructions in 2–4 clocks, enabling 6× performance vs. legacy 80C51 at same frequency. |
| Flash Memory | 1 kB byte-erasable flash organized in 256 B sectors and 16 B pages - allows single-byte erasure for use as non-volatile data storage. |
| RAM | 128 B on-chip RAM - sufficient for stack, variables, and small buffers in deeply embedded real-time control tasks. |
| Operating Voltage | 2.4 V to 3.6 V VDD - enables direct battery operation (e.g., two AA cells); I/O pins tolerate up to 5.5 V, simplifying interface with 5 V peripherals. |
| Max Clock Frequency | 18 MHz - supports high-speed serial communication and responsive real-time control without external PLL. |
| Package | TSSOP14 (SOT402-1), 4.4 mm body width - compact surface-mount footprint ideal for space-constrained PCBs. |
| Temperature Range | −40 °C to +85 °C - qualified for industrial and extended commercial environments. |
Pinout & Package
Package: Plastic thin shrink small outline package; 14 leads; body width 4.4 mm (SOT402-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.2/CIN2A/KBI2 | Port 0 bit 2 / Comparator 2 positive input A / Keypad input 2 | Multi-function pin supporting analog sensing, keyboard scanning, and general I/O - Schmitt-triggered input ensures noise immunity. |
| P0.4/CIN1A/KBI4 | Port 0 bit 4 / Comparator 1 positive input A / Keypad input 4 | Enables dual comparator use with shared reference (CMPREF) and independent signal paths for threshold detection. |
| P0.5/CMPREF/KBI5 | Port 0 bit 5 / Comparator reference (negative) input / Keypad input 5 | Provides programmable analog reference voltage source for both comparators - eliminates need for external resistor divider. |
| P0.6/CMP1/KBI6 | Port 0 bit 6 / Comparator 1 output / Keypad input 6 | Direct comparator output available on I/O pin - enables fast edge-triggered interrupts without software polling. |
| P1.2/T0 | Port 1 bit 2 / Timer 0 external count input or overflow output | Open-drain configuration supports wired-OR logic and level-shifting; usable as PWM output when timer configured in toggle mode. |
| P1.5/RST | Port 1 bit 5 / External reset input | Active-LOW reset pin with internal power-on reset and brownout detection - eliminates external reset IC in most applications. |
| P2.2/MOSI | Port 2 bit 2 / SPI master out slave in | Full-duplex SPI interface pin - supports daisy-chained sensors or EEPROMs with minimal external components. |
| P2.3/MISO | Port 2 bit 3 / SPI master in slave out | Enables bidirectional data transfer in SPI slave mode; compatible with standard SPI peripheral timing requirements. |
| P2.4/SS | Port 2 bit 4 / SPI slave select | Hardware-driven chip select - allows automatic deactivation of SPI peripherals during idle periods to reduce power. |
| P2.5/SPICLK | Port 2 bit 5 / SPI clock | Configurable as master or slave clock source - supports synchronous communication up to system clock frequency. |
| P3.0/XTAL2/CLKOUT | Port 3 bit 0 / Crystal oscillator output / CPU clock divided-by-2 | Provides buffered clock output for test or synchronization; CLKOUT enabled via SFR bit ENCLK - useful for debugging or driving secondary logic. |
| P3.1/XTAL1 | Port 3 bit 1 / Crystal oscillator input | Accepts external crystal (1–18 MHz) or resonator; functions as GPIO if internal RC oscillator selected - increases I/O flexibility. |
| VSS | Ground reference (0 V) | Dedicated ground pin - ensures stable reference for analog comparators and digital logic under mixed-signal operation. |
| VDD | Power supply (2.4–3.6 V) | Single-supply operation with internal voltage monitor - supports graceful shutdown during brownout events. |
Key Features
| Feature | Design Value |
|---|---|
| In-Application Programming (IAP-Lite) | Enables firmware updates and non-volatile parameter storage directly in flash memory during runtime - no external programmer required in field deployments. |
| Configurable port output modes | Each I/O pin supports quasi-bidirectional, open-drain, push-pull, or input-only configuration - optimizes drive strength, power, and interface compatibility per signal. |
| Keypad interrupt with pattern match | Port 0 generates interrupt when pin states match or mismatch a user-defined 4-bit pattern - reduces CPU polling overhead in HMI applications. |
| LED drive capability (20 mA) | All port pins can sink/source up to 20 mA - supports direct LED driving without external transistors in status indicator designs. |
| Controlled slew rate outputs | Outputs feature ≈10 ns minimum ramp time - minimizes EMI emissions and signal integrity issues in dense PCB layouts. |
| Low-power operation | Typical power-down current is 1 µA (with voltage comparators disabled) - extends battery life in always-on sensor nodes and remote controls. |
Applications
| Industrial Sensor Interface | Small Appliance Control |
|---|---|
|
Use Scenario: Monitoring temperature, humidity, or pressure using analog sensors and discrete switches in factory-floor equipment. IC Role / Device Role / Timing Role: Central controller managing ADC-less analog comparators for threshold detection, real-time clock for logging timestamps, and SPI for sensor data acquisition. Use Value: Eliminates external comparators and RTC ICs; 1 kB flash stores calibration coefficients and event logs; 5 V-tolerant I/O interfaces directly with legacy 5 V sensors and displays. |
Use Scenario: Controlling motor speed, display backlight, and user keypad in compact kitchen appliances like coffee makers or rice cookers. IC Role / Device Role / Timing Role: Main MCU handling keypad scan, PWM fan/motor control, LED indicators, and timed cooking sequences via 23-bit system timer. Use Value: Integrated PWM and keypad interrupt reduce external logic; internal RC oscillator removes crystal cost; TSSOP14 footprint fits tight front-panel PCBs. |
| Smart Metering Subsystem | IoT Edge Node Controller |
|
Use Scenario: Supporting tamper detection, pulse counting, and local display in residential electricity/water meters. IC Role / Device Role / Timing Role: Dedicated subsystem MCU performing low-level metering tasks, isolated from main processor, with watchdog supervision and brownout reset. Use Value: Watchdog timer with independent oscillator ensures fail-safe recovery; 128 B RAM retains critical state during brief power dips; flash security bits prevent firmware extraction. |
Use Scenario: Managing environmental sensors, BLE/Wi-Fi module handshaking, and battery charging in battery-powered wireless sensor nodes. IC Role / Device Role / Timing Role: Power-aware coordinator handling wake-up events, sensor sampling, and host interface bridging - leveraging power-down modes and interrupt-driven operation. Use Value: 1 µA power-down current extends 2-year battery life; UART with fractional baud rate generator ensures reliable communication with diverse modules; 2.4–3.6 V range matches Li-ion/Li-Po discharge curves. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC913FDH | Includes UART (TXD/RXD on P1.0/P1.1); lacks T0 on P1.2 and SS on P2.4; same flash/RAM/timers. | Preferred when serial communication (e.g., RS-232/RS-485 interface) is required but SPI slave select and timer 0 output are not needed. | Select P89LPC913FDH if UART functionality is mandatory and SPI SS or T0 PWM output is unnecessary. |
| P89LPC914FDH | Max fosc = 12 MHz; adds UART and T0 on P1.2; retains SS on P2.4; same package and memory. | Suitable for lower-speed, cost-optimized designs where 12 MHz suffices and both UART and T0 are required. | Choose P89LPC914FDH when 12 MHz clock is acceptable and dual serial (UART + SPI) plus timer output are essential. |
Compared with P89LPC912FDH,129, the P89LPC913FDH adds UART at the expense of T0 and SS functionality, while the P89LPC914FDH trades maximum clock speed (12 MHz vs. 18 MHz) for integrated UART and retained T0 - making each variant optimal for distinct I/O and performance trade-offs in resource-constrained systems.
Availability
P89LPC912FDH,129 is available at Aetrix Electronics and suitable for industrial sensor interfaces, small appliance control, smart metering subsystems, and IoT edge node controllers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for P89LPC912FDH,129 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC912FDH,129 belongs to NXP's LPC900 family of low-pin-count, high-integration 8-bit MCUs designed for cost-sensitive, space-constrained embedded control applications demanding reliability, low power, and rapid time-to-market.
FAQ
What is the maximum operating frequency of the P89LPC912FDH,129?
The P89LPC912FDH,129 supports a maximum oscillator frequency of 18 MHz, achievable with external crystal/resonator or internal RC oscillator. At this frequency, its two-clock 80C51 core delivers instruction cycle times of 111–222 ns - six times faster than standard 80C51 devices running at the same clock rate. This enables responsive real-time control without external acceleration circuitry.
Does the P89LPC912FDH,129 include a UART interface?
No, the P89LPC912FDH,129 does not include a UART. Per the official product comparison table, UART functionality is exclusive to P89LPC913FDH and P89LPC914FDH variants. The P89LPC912FDH,129 provides SPI (MOSI/MISO/SPICLK/SS), two 16-bit timers, analog comparators, and keypad interrupt - but no TXD/RXD pins or UART registers.
Can the P89LPC912FDH,129 operate without an external crystal?
Yes, the P89LPC912FDH,129 includes a factory-calibrated internal RC oscillator accurate to ±1 %, allowing full operation without external crystal or resonator. This oscillator is selectable and fine-tunable via flash configuration bits, reducing BOM cost and board area - especially valuable in high-volume consumer and industrial products.
What is the I/O voltage tolerance of the P89LPC912FDH,129?
The I/O pins of the P89LPC912FDH,129 are 5 V tolerant - they may be pulled up to or driven by signals up to 5.5 V, even when VDD is operating at the minimum 2.4 V. This allows direct interfacing with legacy 5 V logic, displays, and sensors without level-shifting components, simplifying design and improving system robustness.
How is non-volatile data storage implemented on the P89LPC912FDH,129?
The P89LPC912FDH,129 uses its 1 kB byte-erasable flash memory for non-volatile data storage via In-Application Programming (IAP-Lite). Individual bytes or pages can be erased and rewritten during runtime, enabling storage of calibration values, device IDs, or operational logs without requiring external EEPROM - reducing component count and cost.
P89LPC912FDH,129 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- SPI
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 12
- Program Memory Size:
- 1KB (1K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC912FDH,129 FAQ
1.How can I place an order for P89LPC912FDH,129 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC912FDH,129 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P89LPC912FDH,129 reliable?
The price and inventory of P89LPC912FDH,129 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P89LPC912FDH,129 is usually 5 days.
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Once your P89LPC912FDH,129 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P89LPC912FDH,129?
For technical support, including P89LPC912FDH,129 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC912FDH,129 requirements.
6.How does Aetrix verify that P89LPC912FDH,129 is sourced from the original manufacturer or authorized distributors?
All P89LPC912FDH,129 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC912FDH,129 meets industry standards.
7.What is the process for return or replacement of P89LPC912FDH,129?
All P89LPC912FDH,129 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC912FDH,129, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC912FDH,129 part is unused and in its original packaging.
Return procedure for P89LPC912FDH,129:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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