NXP Semiconductors P89LPC9151FDH,129
- Part No.:
- P89LPC9151FDH,129
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC9151FDH,129.pdf
- Description:
- IC MCU 8BIT 2KB FLASH 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P89LPC9151FDH,129 from NXP Semiconductors is a low-cost 8-bit microcontroller based on an accelerated two-clock 80C51 core, executing instructions in 2–4 clocks at up to 18 MHz. It integrates 2 kB byte-erasable flash memory, 256-byte RAM, an 8-bit ADC with four analog inputs, dual comparators, and I²C communication. It targets compact embedded control applications such as sensor interface modules and keypad-based industrial controls.
For engineers reviewing the P89LPC9151FDH,129 datasheet, P89LPC9151FDH,129 pinout, P89LPC9151FDH,129 application, or P89LPC9151FDH,129 equivalent, key selection considerations include its 14-pin TSSOP package, 10–12 configurable I/O pins, 2.4–3.6 V operation with 5 V-tolerant I/O, integrated brownout detection, and support for in-application programming (IAP-Lite) of flash memory.
Technical Context
The P89LPC9151FDH,129 implements a high-performance 80C51 CPU architecture delivering six times the instruction throughput of standard 80C51 devices at the same clock frequency-e.g., 111–222 ns instruction cycles at 18 MHz. Its system-level integration includes a 23-bit real-time system timer (7-bit prescaler + 16-bit counter), enhanced UART with fractional baud rate generation, and 400 kHz I²C-bus interface.
It features programmable port output modes (quasi-bidirectional, open-drain, push-pull), Schmitt-trigger inputs on all I/O pins, and hardware-supported keypad interrupt detection across six Port 0 pins. The device supports dynamic clock switching among internal RC oscillator (tunable 20 kHz–18 MHz), watchdog oscillator (~400 kHz), and external clock input-enabling optimized power/performance trade-offs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Accelerated two-clock 80C51 CPU; executes most instructions in 2–4 clocks, enabling 6× speed vs. legacy 80C51 at same frequency. |
| Flash Memory | 2 kB byte-erasable flash organized in 256-byte sectors and 16-byte pages; supports single-byte erasure for non-volatile data storage. |
| ADC/DAC | 4-channel 8-bit ADC with selectable inputs (AD10–AD13); one DAC output (DAC1) on P0.4; two analog comparators with programmable reference and inputs. |
| Timers & Clocking | Two 16-bit counter/timers (T0 active; T1 not available); 23-bit system timer usable as RTC; internal RC oscillator (20 kHz–18 MHz) with clock doubler option. |
| I/O & Power | 14-pin TSSOP package with ≥10 user-configurable I/O pins; operates from 2.4 V to 3.6 V; all I/O pins 5 V tolerant (up to 5.5 V); typical power-down current = 1 μA. |
| Communication | Enhanced UART with break detect, framing error detection, and automatic address recognition; 400 kHz I²C-bus interface (SCL/SDA on P1.2/P1.3); no SPI (exclusive to P89LPC9161). |
| Interrupt System | Four priority levels; six keypad interrupt inputs (KBI0–KBI5) on Port 0; two external interrupts (INT0/INT1); port pattern-match interrupt capability. |
Pinout & Package
Package: Plastic thin shrink small outline package; 14 leads; body width 4.4 mm (SOT402-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0/CMP2/KBI0 | Port 0 bit 0 / Comparator 2 output / Keypad input 0 | Configurable I/O with Schmitt trigger; supports comparator output or keyboard scan; used in keypad matrix row/column detection. |
| P0.1/CIN2B/KBI1/AD10 | Port 0 bit 1 / Comp2+ B / Keypad input 1 / ADC channel 0 | Multi-function analog/digital pin; enables simultaneous analog sensing and keypad scanning without external mux. |
| P0.2/CIN2A/KBI2/AD11 | Port 0 bit 2 / Comp2+ A / Keypad input 2 / ADC channel 1 | Shared analog input and keyboard interrupt source; simplifies mixed-signal front-end design in sensor nodes. |
| P0.3/CIN1B/KBI3/AD12 | Port 0 bit 3 / Comp1+ B / Keypad input 3 / ADC channel 2 | High-current sourcing I/O (20 mA); suitable for driving LEDs or small relays while retaining analog sensing capability. |
| P0.4/CIN1A/KBI4/DAC1/AD13 | Port 0 bit 4 / Comp1+ A / Keypad input 4 / DAC output / ADC channel 3 | Unique dual-direction analog node: accepts analog input (AD13), generates analog output (DAC1), and serves as KBI4-ideal for closed-loop control. |
| P0.5/CMPREF/KBI5/CLKIN | Port 0 bit 5 / Comp reference / Keypad input 5 / External clock input | Provides negative reference for both comparators; also accepts external timing source or functions as sixth keypad line. |
| P1.0/TXD | Port 1 bit 0 / UART transmit output | Open-drain capable; directly interfaces with RS-232 level shifters or TTL logic; supports asynchronous serial debug and telemetry. |
| P1.1/RXD | Port 1 bit 1 / UART receive input | Schmitt-triggered input ensures noise immunity on serial bus; compatible with 3.3 V and 5 V logic families. |
| P1.2/T0/SCL | Port 1 bit 2 / Timer 0 I/O / I²C clock | Open-drain configuration required for I²C SCL; also serves as timer overflow toggle or external count input-reducing pin count in timing-critical designs. |
| P1.3/INT0/SDA | Port 1 bit 3 / External interrupt 0 / I²C data | Open-drain I²C SDA with built-in interrupt capability; enables wake-up from power-down on I²C activity or external event. |
| P1.4/INT1 | Port 1 bit 4 / External interrupt 1 | High-current sourcing I/O (20 mA); supports direct connection to mechanical switches or optocouplers without external pull-ups. |
| P1.5/RST | Port 1 bit 5 / Reset input | Active-low reset with on-chip power-on reset circuitry; eliminates need for external RC reset network in cost-sensitive designs. |
| VSS | Ground | 0 V reference for analog and digital domains; decoupling capacitor placement near this pin critical for ADC accuracy and EMI reduction. |
| VDD | Power supply | 2.4–3.6 V supply for full functionality; supports battery-powered operation; internal voltage monitor enables graceful shutdown during brownout. |
Key Features
| Feature | Design Value |
|---|---|
| Byte-erasable flash memory | Enables use of code space as non-volatile data storage (e.g., calibration coefficients, device IDs) without requiring external EEPROM. |
| Integrated 8-bit ADC + DAC + dual comparators | Reduces BOM count by eliminating discrete analog front-end components in sensor signal conditioning and feedback control loops. |
| Programmable port output types | Allows per-pin configuration as quasi-bidirectional, open-drain, or push-pull-optimizing drive strength and bus compatibility across mixed-voltage systems. |
| On-chip RC oscillator with clock doubler | Eliminates external crystal/capacitors for timing; tunable range (20 kHz–18 MHz) supports both ultra-low-power sleep and high-speed processing modes. |
| Keypad interrupt with pattern match | Hardware-accelerated key scan reduces CPU overhead; port-level pattern matching enables wake-up from power-down on specific keypress combinations. |
| Four interrupt priority levels | Supports deterministic real-time response in multi-tasking firmware-critical for time-sensitive I/O handling in industrial HMI and safety monitoring. |
Applications
| Industrial Sensor Node | Keypad-Controlled HMI |
|---|---|
Use Scenario: Compact environmental sensor module measuring temperature, humidity, and analog gas concentration signals. IC Role / Device Role / Timing Role: Central controller performing ADC sampling, analog comparator thresholding, I²C communication with sensor ICs, and UART telemetry reporting. Use Value: Integrated 8-bit ADC with four channels and DAC output enables direct analog interfacing; 2 kB flash stores sensor calibration data and firmware updates via IAP-Lite. | Use Scenario: Front-panel interface for HVAC controllers or access terminals with 6-key membrane keypad and LED status indicators. IC Role / Device Role / Timing Role: Keypad scanner and display driver managing key debouncing, interrupt-driven wake-up, and GPIO-controlled LED feedback. Use Value: Six dedicated KBI inputs on Port 0 eliminate external interrupt expanders; high-current I/O pins (20 mA) drive LEDs directly without buffer transistors. |
| Low-Power Metering Module | Legacy 8051 Upgrade Platform |
Use Scenario: Battery-operated utility meter logging voltage/current samples and transmitting via UART to concentrator. IC Role / Device Role / Timing Role: Low-power data acquisition unit using RTC timer for periodic wake-up, ADC for analog measurement, and UART for burst transmission. Use Value: 1 μA typical power-down current extends battery life; brownout detection prevents corrupted flash writes during voltage sag; 5 V-tolerant I/O simplifies interface with legacy metering peripherals. | Use Scenario: Drop-in replacement for aging 80C51-based control boards in factory automation equipment. IC Role / Device Role / Timing Role: Pin-compatible software upgrade path preserving existing PCB layout and firmware structure with minimal rework. Use Value: Accelerated 2-clock core delivers 6× performance at same clock frequency; identical SFR map and instruction set ensure backward compatibility while reducing cycle count per task. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC9161FDH | 16-pin TSSOP; adds SPI interface (MOSI/MISO/SPICLK/SS); same 2 kB flash, 256-byte RAM, and ADC/DAC features. | Required when SPI peripheral connectivity is needed (e.g., SD card, display driver, or sensor fusion with SPI sensors). | Select P89LPC9161FDH only if SPI is mandatory; otherwise P89LPC9151FDH offers lower pin count and reduced board area. |
| P89LPC9171FDH | 16-pin TSSOP; adds Timer 1 (T1) and CLKOUT pin (P0.7); retains all P89LPC9151FDH peripherals plus SPI (like P89LPC9161FDH). | Suitable for designs requiring dual 16-bit timers or precise clock distribution (e.g., synchronized sampling or master clock generation). | Choose P89LPC9171FDH when Timer 1 or clock output functionality is essential; P89LPC9151FDH remains optimal for cost- and size-constrained single-timer applications. |
Compared with P89LPC9161FDH and P89LPC9171FDH, the P89LPC9151FDH provides the smallest footprint (14-pin TSSOP) and lowest component count for applications that do not require SPI or Timer 1-making it ideal for ultra-compact, cost-sensitive embedded control where I²C and single-timer operation suffice.
Availability
P89LPC9151FDH,129 is available at Aetrix Electronics and suitable for industrial sensor nodes, keypad-based HMIs, low-power metering modules, legacy 8051 upgrades, and compact embedded control systems requiring stable component supply and long-term manufacturability.
Supply support for P89LPC9151FDH,129 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC9151FDH,129 belongs to NXP's LPC900 family of enhanced 80C51 microcontrollers, designed specifically for cost-sensitive, space-constrained embedded systems requiring high integration, low power, and robust analog/mixed-signal capabilities.
FAQ
What is the maximum operating frequency of the P89LPC9151FDH,129?
The P89LPC9151FDH,129 supports a maximum operating frequency of 18 MHz. This applies whether using the internal RC oscillator (with optional clock doubler), external crystal, or external clock input. At 18 MHz, instruction cycle times range from 111 ns to 222 ns-six times faster than a standard 80C51 running at the same frequency. The P89LPC9151FDH,129 datasheet specifies this limit across the full −40 °C to +85 °C temperature range.
Does the P89LPC9151FDH,129 support in-system programming (ISP)?
Yes, the P89LPC9151FDH,129 supports In-System Programming (ISP) via its UART interface using standard commercial EPROM programmers. Flash memory can be programmed while the device is soldered onto the target board, enabling field firmware updates and simplified manufacturing. The P89LPC9151FDH,129 also supports In-Application Programming (IAP-Lite), allowing selected code memory sectors to be rewritten during runtime for data logging or parameter storage.
How many I/O pins does the P89LPC9151FDH,129 provide in its TSSOP14 package?
The P89LPC9151FDH,129 provides a minimum of 10 general-purpose I/O pins and up to 12 I/O pins when using on-chip oscillator and reset options. This includes six pins on Port 0 (P0.0–P0.5), five pins on Port 1 (P1.0–P1.4), and the RST pin (P1.5) configured as input-only. All I/O pins are 5 V tolerant (up to 5.5 V) and support multiple output configurations-quasi-bidirectional, open-drain, or push-pull-as defined in the P89LPC9151FDH,129 configuration registers.
What analog peripherals are integrated into the P89LPC9151FDH,129?
The P89LPC9151FDH,129 integrates a 4-channel 8-bit ADC (AD10–AD13), one DAC output (DAC1 on P0.4), and two analog comparators (CMP1 and CMP2) with selectable positive/negative inputs and shared reference (CMPREF). The ADC supports single-ended and differential modes; comparators feature hysteresis control and interrupt generation. These peripherals are fully accessible through dedicated SFRs and require no external components-enabling self-contained analog signal acquisition and conditioning in the P89LPC9151FDH,129.
Is the P89LPC9151FDH,129 pin-compatible with other members of the LPC91x family?
No, the P89LPC9151FDH,129 is not pin-compatible with P89LPC9161FDH or P89LPC9171FDH due to differing package sizes (14-pin TSSOP vs. 16-pin TSSOP) and distinct pin allocations. While all three share functional similarities-including flash size, ADC, DAC, and I²C-the P89LPC9151FDH,129 lacks SPI and Timer 1 pins present in the 16-pin variants. PCB layout must be redesigned to migrate between these variants; they are functionally related but not drop-in replacements.
P89LPC9151FDH,129 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 12
- Program Memory Size:
- 2KB (2K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 4x8b; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC9151FDH,129 FAQ
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6.How does Aetrix verify that P89LPC9151FDH,129 is sourced from the original manufacturer or authorized distributors?
All P89LPC9151FDH,129 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC9151FDH,129 meets industry standards.
7.What is the process for return or replacement of P89LPC9151FDH,129?
All P89LPC9151FDH,129 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC9151FDH,129, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC9151FDH,129 part is unused and in its original packaging.
Return procedure for P89LPC9151FDH,129:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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