My Inquiry
My Account
NXP Semiconductors P89LPC9161FDH,129
- Part No.:
- P89LPC9161FDH,129
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC9161FDH,129.pdf
- Description:
- IC MCU 8BIT 2KB FLASH 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,155
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
P89LPC9161FDH,129 from NXP Semiconductors is an 8-bit accelerated 2-clock 80C51 microcontroller in TSSOP16 package, featuring 2 kB byte-erasable flash memory, 256-byte RAM, 4-channel 8-bit ADC, single DAC output, two 16-bit timers, and integrated SPI/I²C/UART interfaces. It operates from 2.4 V to 3.6 V with 5 V-tolerant I/O and targets low-cost embedded control in space-constrained industrial and consumer systems.
For engineers reviewing the P89LPC9161FDH,129 datasheet, P89LPC9161FDH,129 pinout, P89LPC9161FDH,129 application, or P89LPC9161FDH,129 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases, and confirmed alternative options - all grounded in the official NXP Rev. 02 datasheet (9 Feb 2010) and functional diagrams for the P89LPC9161 variant.
Technical Context
The P89LPC9161FDH,129 implements a high-performance 80C51 core executing instructions in 2–4 clocks (6× speed of standard 80C51 at same frequency), with on-chip RC oscillator (20 kHz–18 MHz), programmable slew-rate outputs, and four interrupt priority levels. Its architecture integrates analog peripherals including dual comparators with selectable inputs and reference, plus port-level pattern-match interrupt capability on Port 0.
Unlike the P89LPC9151 and P89LPC9171 variants, the P89LPC9161FDH,129 includes a full 4-wire SPI interface (MOSI/MISO/SPICLK/SS) mapped to Port 2 pins, while omitting Timer 1 and Port 0.0/CMP2/KBI0 functionality. It supports In-Application Programming (IAP-Lite) and uses a dedicated watchdog oscillator (±5% accuracy, no external components) for fail-safe reset management.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Accelerated 2-clock 80C51 CPU; executes all instructions except multiply/divide in 111–222 ns at 18 MHz - enables higher throughput at lower clock frequency, reducing EMI and power consumption. |
| Memory | 2 kB byte-erasable flash (256-byte sectors, 16-byte pages) + 256-byte RAM; allows non-volatile data storage in code memory without external EEPROM. |
| Analog Peripherals | 4-input multiplexed 8-bit ADC + single DAC output + two analog comparators with configurable inputs and reference source - supports sensor interfacing and closed-loop analog control. |
| Communication Interfaces | Enhanced UART (fractional baud rate, break detect), 400 kHz I²C-bus, and full-duplex 4-wire SPI - enables robust multi-protocol connectivity in mixed-signal systems. |
| Power & I/O | 2.4 V–3.6 V operation; 5 V-tolerant I/O pins; 12–14 usable I/O (depending on oscillator/reset configuration); typical power-down current = 1 µA - suitable for battery-powered and low-power industrial nodes. |
| Timing & Reset | 23-bit system timer (7-bit prescaler + 16-bit counter) usable as RTC; on-chip power-on reset and brownout detection; software reset support - eliminates need for external reset ICs and simplifies BOM. |
Pinout & Package
Package: TSSOP16 (SOT403-1), plastic thin shrink small outline package, 16 leads, 4.4 mm body width.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (P0.1) | CIN2B / KBI1 / AD10 | Comparator 2 positive input B, keypad interrupt 1, ADC1 channel 0 - enables analog threshold detection and matrix keypad scanning without external logic. |
| 2 (P0.2) | CIN2A / KBI2 / AD11 | Comparator 2 positive input A, keypad interrupt 2, ADC1 channel 1 - supports differential comparator mode and dual-key sensing per scan cycle. |
| 3 (P1.5) | RST | Active-low reset input; also forces ISP mode during power-on - provides hardware reset path and in-system programming entry without dedicated programmer header. |
| 4 (VSS) | Ground | 0 V reference for analog and digital domains - requires low-impedance connection to minimize noise coupling between ADC and digital logic. |
| 5 (P2.3) | MISO | Master In Slave Out for SPI; bidirectional with internal pull-up - allows daisy-chained slave configurations and reduces external pull-up requirements. |
| 6 (P2.2) | MOSI | Master Out Slave In for SPI; output when master, input when slave - supports full-duplex communication with sensors or flash memory. |
| 7 (P1.3) | INT0 / SDA | External interrupt 0 input and I²C serial data line - enables event-driven wake-up and multi-device bus arbitration in shared I²C environments. |
| 8 (P1.2) | T0 / SCL | Timer 0 external count input or overflow output, and I²C serial clock - permits hardware timer gating and synchronous bus timing without CPU overhead. |
| 9 (P1.1) | RXD | UART receiver input with framing error detection - supports reliable asynchronous communication with modems or host controllers. |
| 10 (P1.0) | TXD | UART transmitter output with automatic address detection - enables multi-drop RS-485-style networks using standard UART hardware. |
| 11 (P2.5) | SPICLK | SPI clock input/output; output when master, input when slave - defines bit rate and synchronizes data transfers across SPI peripherals. |
| 12 (VDD) | Power supply | 2.4 V–3.6 V supply for all operating modes including idle and power-down - decoupling capacitor required within 10 mm of pin for stable ADC performance. |
| 13 (P0.5) | CMPREF / KBI5 / CLKIN | Comparator reference (negative) input, keypad interrupt 5, external clock input - allows user-defined voltage thresholds and external crystal or oscillator drive. |
| 14 (P0.4) | CIN1A / KBI4 / DAC1 / AD13 | Comparator 1 positive input A, keypad interrupt 4, DAC output, ADC1 channel 3 - enables simultaneous analog output generation and input sampling on same pin. |
| 15 (P0.3) | CIN1B / KBI3 / AD12 | Comparator 1 positive input B, keypad interrupt 3, ADC1 channel 2 - supports dual-comparator window detection and 4×4 keypad row/column decoding. |
| 16 (P2.4) | SS | SPI slave select input; active-low - controls device enable state in multi-slave SPI buses and prevents spurious data reception. |
Key Features
| Feature | Design Value |
|---|---|
| In-Application Programming (IAP-Lite) | Enables firmware updates and non-volatile parameter storage directly in flash memory during runtime - eliminates need for external EEPROM and reduces system cost. |
| Configurable port output types | Quasi-bidirectional, open-drain, push-pull, and input-only modes per pin - allows direct LED driving, I²C bus termination, and level-shifting without external components. |
| Controlled slew-rate outputs | ~10 ns minimum ramp time on all port outputs - reduces electromagnetic interference in densely packed PCB layouts and meets Class B EMC requirements. |
| Port input pattern match interrupt | Generates interrupt when Port 0 pins match or mismatch a programmable 6-bit pattern - enables low-power wake-up on specific keypress combinations or sensor state transitions. |
| High-accuracy internal RC oscillator | Calibrated ±5% over temperature and voltage; supports clock doubler option - eliminates external crystal for cost-sensitive applications while maintaining UART timing integrity. |
Applications
| Industrial Sensor Node | Smart Keypad Interface |
|---|---|
|
Use Scenario: Compact environmental monitoring unit measuring temperature, humidity, and light via analog sensors, transmitting data over UART to gateway. IC Role / Device Role / Timing Role: Central controller managing ADC sampling, DAC-based reference generation, UART transmission, and low-power sleep/wake cycles. Use Value: Integrated 8-bit ADC, DAC, and fractional baud rate generator eliminate 3 external ICs; 1 µA power-down current extends battery life to >2 years on coin cell. |
Use Scenario: 5×5 membrane keypad in HVAC control panel with backlight dimming and tactile feedback. IC Role / Device Role / Timing Role: Keypad scanner using Port 0 KBI inputs and Port 1/2 for row/column drive; PWM-capable Timer 0 controls LED brightness. Use Value: Hardware keypad interrupt engine scans 25 keys in <100 µs; programmable port output types drive LEDs directly without current-limiting resistors. |
| Embedded Power Monitor | I²C/SPI Bridge Module |
|
Use Scenario: AC-DC adapter with real-time voltage/current measurement, overvoltage protection, and status reporting via I²C to host MCU. IC Role / Device Role / Timing Role: Analog front-end controller performing ADC conversions, comparator-based fault detection, and I²C slave communication. Use Value: Dual analog comparators provide independent OV/UV trip points; 400 kHz I²C interface ensures fast status polling without blocking main processor. |
Use Scenario: Protocol translator converting I²C commands from host to SPI writes for flash memory or display driver. IC Role / Device Role / Timing Role: I²C slave receiving commands and SPI master executing peripheral writes; uses UART for debug logging. Use Value: Simultaneous I²C slave and SPI master operation enables seamless bridging; on-chip RC oscillator avoids clock domain conflicts between buses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC9151FDH | 14-pin TSSOP, no SPI interface, no Port 2, only 10 I/O pins minimum; lacks MOSI/MISO/SPICLK/SS pins. | Targeted at ultra-low-pin-count designs where SPI is unnecessary and board space is critical. | Select when SPI is not required and PCB footprint must be minimized - but verify I²C/UART bandwidth suffices for data throughput needs. |
| P89LPC9171FDH | 16-pin TSSOP with Timer 1, Port 0.0/CMP2/KBI0, Port 0.7/T1/CLKOUT, and Port 2.2 - adds extra timer and comparator output not present in P89LPC9161FDH,129. | Suitable for applications requiring dual 16-bit timers (e.g., motor phase control) or additional comparator output for drive signal conditioning. | Choose when Timer 1 or CMP2 output is essential; note that P89LPC9171FDH requires different firmware initialization for extended peripherals. |
Compared with P89LPC9151FDH and P89LPC9171FDH, the P89LPC9161FDH,129 uniquely balances SPI capability, 12+ I/O count, and compact TSSOP16 packaging - making it optimal for mid-complexity sensor hubs and protocol bridges where both serial interfaces and analog integration are required without timer expansion.
Availability
P89LPC9161FDH,129 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart keypad interfaces, embedded power monitors, and I²C/SPI bridge modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for P89LPC9161FDH,129 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC9161FDH,129 belongs to NXP's LPC900 family of enhanced 80C51 microcontrollers, designed specifically for cost-sensitive, space-constrained embedded control applications requiring integrated analog peripherals and multiple serial interfaces.
FAQ
What is the maximum operating frequency of the P89LPC9161FDH,129?
The P89LPC9161FDH,129 supports a maximum operating frequency of 18 MHz, achievable using either the internal RC oscillator (with optional clock doubler) or an external crystal/clock source. At 18 MHz, its accelerated 2-clock core delivers instruction cycle times of 111–222 ns - six times faster than a standard 80C51 at the same clock rate. This enables deterministic real-time response in time-critical control loops without increasing EMI.
Does the P89LPC9161FDH,129 support in-system programming (ISP)?
Yes, the P89LPC9161FDH,129 supports In-System Programming via its UART interface using the built-in bootloader. During power-on, asserting LOW on the P1.5/RST pin forces ISP mode, allowing firmware updates without removing the device from the PCB. The P89LPC9161FDH,129 also supports Serial Flash In-Circuit Programming (ICP) with commercial EPROM programmers, and flash security bits prevent unauthorized readout of application code.
How many I/O pins are available on the P89LPC9161FDH,129 in standard configuration?
The P89LPC9161FDH,129 provides a minimum of 12 I/O pins and up to 14 I/O pins when using on-chip oscillator and reset options. This includes 5-bit Port 0 (P0.1–P0.5), 4-bit Port 1 (P1.0–P1.3), and 4-bit Port 2 (P2.2–P2.5), with P1.5 reserved for reset and VDD/VSS excluded from I/O count. All I/O pins are 5 V tolerant and support programmable output configurations including open-drain for I²C bus compatibility.
What analog peripherals are integrated into the P89LPC9161FDH,129?
The P89LPC9161FDH,129 integrates a 4-channel 8-bit ADC (AD10–AD13), a single DAC output (DAC1 on P0.4), and two analog comparators (CMP1 and CMP2) with selectable positive/negative inputs and reference sources. The ADC supports burst mode and boundary detection, while comparators feature interrupt capability and can operate independently of the CPU - enabling low-latency analog event handling in power-constrained systems.
Is the P89LPC9161FDH,129 pin-compatible with other devices in the LPC91x family?
No, the P89LPC9161FDH,129 is not pin-compatible with P89LPC9151FDH (TSSOP14) or P89LPC9171FDH (TSSOP16 with different pin assignments). While all three share the TSSOP16 footprint, P89LPC9161FDH,129 assigns SPI signals (MOSI/MISO/SPICLK/SS) to Port 2 pins, whereas P89LPC9171FDH uses Port 2.2 for general I/O and adds T1/CLKOUT on P0.7. PCB layout must be specific to the P89LPC9161FDH,129 pinout.
P89LPC9161FDH,129 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 14
- Program Memory Size:
- 2KB (2K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 4x8b; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC9161FDH,129 FAQ
1.How can I place an order for P89LPC9161FDH,129 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC9161FDH,129 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P89LPC9161FDH,129 reliable?
The price and inventory of P89LPC9161FDH,129 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P89LPC9161FDH,129 is usually 5 days.
3.What payment methods are accepted for P89LPC9161FDH,129?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P89LPC9161FDH,129 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P89LPC9161FDH,129?
P89LPC9161FDH,129 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P89LPC9161FDH,129 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P89LPC9161FDH,129?
For technical support, including P89LPC9161FDH,129 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC9161FDH,129 requirements.
6.How does Aetrix verify that P89LPC9161FDH,129 is sourced from the original manufacturer or authorized distributors?
All P89LPC9161FDH,129 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC9161FDH,129 meets industry standards.
7.What is the process for return or replacement of P89LPC9161FDH,129?
All P89LPC9161FDH,129 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC9161FDH,129, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC9161FDH,129 part is unused and in its original packaging.
Return procedure for P89LPC9161FDH,129:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
P89LPC9161FDH,129 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
