NXP Semiconductors P89LPC916FDH,118
- Part No.:
- P89LPC916FDH,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC916FDH,118.pdf
- Description:
- IC MCU 8BIT 2KB FLASH 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P89LPC916FDH,118 from NXP Semiconductors is an 8-bit accelerated two-clock 80C51 microcontroller in a 16-pin TSSOP package, featuring 2 kB flash code memory, 256-byte RAM, 4-channel 8-bit ADC, DAC output, SPI interface, and 5 keypad interrupt inputs. It operates from 2.4 V to 3.6 V with 5 V-tolerant I/O, enabling compact low-power embedded control in space-constrained industrial sensors and smart peripherals.
For engineers reviewing the P89LPC916FDH,118 datasheet, P89LPC916FDH,118 pinout, P89LPC916FDH,118 application, or P89LPC916FDH,118 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases, and confirmed alternative parts - all grounded in NXP's Rev. 05 product data sheet dated 15 December 2009.
Technical Context
The P89LPC916FDH,118 implements a high-performance 80C51 core executing instructions in two to four clocks-six times faster than standard 80C51 at the same frequency-enabling 111 ns to 222 ns instruction cycles at 18 MHz. Its architecture integrates on-chip peripherals including UART with fractional baud rate generator, I²C, and SPI (exclusive to P89LPC916), eliminating external bus logic.
It features dual 16-bit timers (Timer 0 only; Timer 1 absent per Table 1), a 23-bit system timer usable as RTC, analog comparators with selectable reference, and programmable port configurations (quasi-bidirectional, open-drain, push-pull). The internal RC oscillator-factory-calibrated to ±1% and fine-tunable-supports operation without external crystals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Accelerated two-clock 80C51 CPU delivering six-fold throughput vs. standard 80C51 at same clock frequency. |
| Flash Memory | 2 kB byte-erasable flash organized in 256-byte sectors; supports In-Application Programming (IAP-Lite) for firmware updates and non-volatile data storage. |
| ADC/DAC | 4-input multiplexed 8-bit ADC with dedicated channels AD10–AD13; single DAC1 analog output on P0.4. |
| Communication Interfaces | SPI master/slave (P2.2/MOSI, P2.3/MISO, P2.4/SS, P2.5/SPICLK); enhanced UART with break detect and automatic address detection; I²C (SCL/SDA on P1.2/P1.3). |
| Power & I/O | 2.4 V to 3.6 V VDD operation; all I/O pins 5 V tolerant (up to 5.5 V); 14 usable I/O pins when internal oscillator and reset are enabled. |
| Timers & Clock | Two 16-bit counter/timers (Timer 0 only; Timer 1 not present); 23-bit system timer with RTC capability; internal RC oscillator ±1% accuracy, fine-tunable. |
| Interrupt System | Four priority levels; five dedicated keypad interrupt inputs (KBI0–KBI4) on Port 0; external INT0/INT1; UART, timer, ADC, and port match interrupts. |
Pinout & Package
Package: TSSOP16 (plastic thin shrink small outline package; 16 leads; body width 4.4 mm; SOT403-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: P0.1/CIN2B/KBI1/AD10 | Port 0 bit 1 / Comparator 2 positive input B / Keypad input 1 / ADC channel 0 | Multi-function pin supporting analog sensing, keyboard scanning, and comparator input; Schmitt-triggered input. |
| 2: P0.2/CIN2A/KBI2/AD11 | Port 0 bit 2 / Comparator 2 positive input A / Keypad input 2 / ADC channel 1 | Enables differential analog comparison (CIN2A/CIN2B) and simultaneous 8-bit ADC sampling across four channels. |
| 3: P2.4/SS | Port 2 bit 4 / SPI slave select | Active-low SPI chip select; enables multi-device SPI bus sharing; open-drain capable for wired-OR configuration. |
| 4: P0.3/CIN1B/KBI3/AD12 | Port 0 bit 3 / Comparator 1 positive input B / Keypad input 3 / ADC channel 2 | Supports dual independent analog comparators (CMP1/CMP2) with shared reference (CMPREF on P0.5). |
| 5: P1.5/RST | Port 1 bit 5 / External reset input | Active-low reset; also forces ISP mode during power-on; requires external hold circuit above 12 MHz oscillator use. |
| 6: P0.4/CIN1A/KBI4/AD13/DAC1 | Port 0 bit 4 / Comparator 1 positive input A / Keypad input 4 / ADC channel 3 / DAC output | Single-pin analog output (DAC1) for closed-loop control; shares pin with ADC input and comparator function. |
| 7: VSS | Ground reference | 0 V return path for digital and analog domains; decoupling capacitor placement critical for ADC/SPI noise immunity. |
| 8: P0.5/CMPREF/KBI5/CLKIN | Port 0 bit 5 / Comparator reference input / Keypad input 5 / External clock input | Provides negative reference for both comparators; accepts external crystal or clock source up to 18 MHz. |
| 9: P2.3/MISO | Port 2 bit 3 / SPI master-in slave-out | Configurable as input (master) or output (slave); supports full-duplex SPI communication with P2.2/MOSI and P2.5/SPICLK. |
| 10: VDD | Power supply | 2.4 V–3.6 V main supply; powers core, peripherals, and I/O; 5 V-tolerant I/O allows mixed-voltage interfacing. |
| 11: P2.2/MOSI | Port 2 bit 2 / SPI master-out slave-in | Drives data to slave devices; open-drain option supports level shifting in multi-voltage systems. |
| 12: P2.5/SPICLK | Port 2 bit 5 / SPI clock | Master-generated clock signal; configurable polarity/phase; synchronizes all SPI data transfers. |
| 13: P1.3/INT0/SDA | Port 1 bit 3 / External interrupt 0 / I²C serial data | Open-drain bidirectional I²C data line; doubles as edge-triggered interrupt source for event-driven wake-up. |
| 14: P1.0/TXD | Port 1 bit 0 / UART transmit output | Asynchronous serial output; supports fractional baud rate generation for precise timing across wide frequency ranges. |
| 15: P1.2/T0/SCL | Port 1 bit 2 / Timer 0 external count input / I²C serial clock | Open-drain I²C clock line; also serves as Timer 0 gate or counter input for pulse-width measurement. |
| 16: P1.1/RXD | Port 1 bit 1 / UART receive input | Asynchronous serial input with framing error detection and break detect; enables robust host-to-peripheral communication. |
Key Features
| Feature | Design Value |
|---|---|
| In-Application Programming (IAP-Lite) | Enables field firmware updates and secure non-volatile data storage in flash without external programmer; supports byte-level erase. |
| 5 V-tolerant I/O pins | Allows direct interfacing with legacy 5 V logic and sensors without level shifters, reducing BOM cost and board area. |
| Programmable slew-rate outputs | Controlled ~10 ns minimum ramp time reduces EMI emissions, easing EMC compliance in industrial and consumer applications. |
| Low-power operation modes | Idle and two power-down modes; typical power-down current is 1 µA (with voltage comparators disabled), extending battery life. |
| Keypad interrupt with pattern match | Port 0 pins generate interrupt on rising/falling edge or value match/non-match, enabling responsive key matrix scanning with zero CPU overhead. |
| Internal RC oscillator (±1%) | Eliminates external crystal and load capacitors; factory-trimmed and software-fine-tunable for cost-sensitive, space-constrained designs. |
Applications
| Industrial Sensor Node | Smart Home Keypad Controller |
|---|---|
|
Use Scenario: Compact environmental sensor node measuring temperature, humidity, and gas concentration using analog sensors and driving local LED indicators. IC Role / Device Role / Timing Role: Central controller executing sensor acquisition via 4-channel ADC, processing readings, generating DAC output for analog actuator control, and communicating via UART to gateway. Use Value: Integrated ADC/DAC, SPI for sensor expansion, and 5 V-tolerant I/O eliminate external signal conditioning ICs and level shifters, reducing total solution size by >30%. |
Use Scenario: Wall-mounted keypad with 5-key matrix, backlight control, and RS-485 communication to HVAC controller. IC Role / Device Role / Timing Role: Keypad scan engine using KBI0–KBI4; UART with fractional baud rate generator for reliable 9600 bps RS-485 link; LED drive capability (20 mA) for backlight. Use Value: Dedicated keypad interrupt inputs reduce polling overhead; internal RC oscillator ensures stable timing without crystal, lowering component count and assembly cost. |
| Low-Power Metering Module | Embedded I²C Peripheral Bridge |
|
Use Scenario: Battery-powered utility meter logging voltage/current samples and transmitting data over LoRaWAN via UART-connected modem. IC Role / Device Role / Timing Role: Data acquisition unit with 23-bit system timer used as RTC for timestamping; power-down mode activated between samples to achieve µA-level sleep current. Use Value: 1 µA typical power-down current extends 10-year battery life; brownout detect with interrupt enables graceful shutdown before data corruption. |
Use Scenario: Protocol translator converting I²C commands from MCU host to SPI-configured display driver and ADC. IC Role / Device Role / Timing Role: Dual-interface bridge: I²C slave (SDA/SCL on P1.3/P1.2) receives commands; SPI master (P2.2–P2.5) configures downstream peripherals. Use Value: Hardware-accelerated SPI and I²C eliminate bit-banging overhead; separate SFR-controlled clock dividers allow independent timing for each bus. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC915FDH | 14-pin TSSOP; no SPI; 6 keypad interrupts; lacks comparator 2 output (CMP2) and DAC1 on P0.4. | Lower I/O count and peripheral set; suitable for simpler keypad-only or basic ADC tasks without SPI or DAC requirements. | Select when SPI interface and DAC output are unnecessary and PCB space is constrained to 14-pin footprint. |
| P89LPC917FDH | 16-pin TSSOP; adds Timer 1, CLKOUT, INT1, CMP2 output, and KBI7; retains SPI but omits DAC1 on P0.4. | Enhanced timing and interrupt capability for real-time control; trade-off is loss of integrated DAC for analog output generation. | Choose when additional timer precision, external clock distribution (CLKOUT), or extra interrupt sources outweigh need for DAC functionality. |
Compared with P89LPC915FDH, the P89LPC916FDH,118 adds SPI and retains DAC1 but reduces keypad inputs from six to five; versus P89LPC917FDH, it sacrifices Timer 1 and CLKOUT to preserve DAC1-making it the only variant offering both SPI and integrated DAC in the family.
Availability
P89LPC916FDH,118 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home keypad controllers, low-power metering modules, and embedded I²C peripheral bridges requiring stable component supply and long-term manufacturability.
Supply support for P89LPC916FDH,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC916FDH,118 belongs to NXP's LPC900 family of 8-bit microcontrollers designed for cost-sensitive, space-constrained embedded control where integration of analog peripherals, low-power operation, and simplified BOM are critical.
FAQ
What is the maximum operating frequency of the P89LPC916FDH,118?
The P89LPC916FDH,118 supports a maximum oscillator frequency of 18 MHz, delivering instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide. This is achieved using either the internal RC oscillator (±1% calibrated) or an external crystal/clock source connected to P0.5/CLKIN.
Does the P89LPC916FDH,118 include a DAC, and on which pin is it available?
Yes, the P89LPC916FDH,118 includes a single DAC output (DAC1) available exclusively on pin P0.4, which is shared with ADC channel 3 (AD13), comparator 1 input A (CIN1A), and keypad interrupt input KBI4. This pin supports simultaneous analog output and input functions under software control.
How many keypad interrupt inputs does the P89LPC916FDH,118 support, and which pins are assigned?
The P89LPC916FDH,118 supports exactly five keypad interrupt inputs: KBI0 through KBI4. These are mapped to P0.0, P0.1, P0.2, P0.3, and P0.4 respectively. Unlike P89LPC915 (6 inputs) or P89LPC917 (7 inputs), the P89LPC916FDH,118 omits KBI5 and KBI6 to accommodate SPI functionality within the 16-pin TSSOP package.
Is the P89LPC916FDH,118 pin-compatible with other members of the LPC915/916/917 family?
No, the P89LPC916FDH,118 is not pin-compatible with P89LPC915FDH (14-pin TSSOP) or P89LPC917FDH (16-pin TSSOP with different pin assignments). While all three use TSSOP packages, P89LPC916FDH,118 assigns SPI signals (MOSI/MISO/SS/SPICLK) to Port 2 pins, whereas P89LPC917FDH uses those pins for Timer 1 and CLKOUT - requiring PCB redesign for substitution.
What power supply voltage range is supported by the P89LPC916FDH,118, and are its I/O pins 5 V tolerant?
The P89LPC916FDH,118 operates from 2.4 V to 3.6 V on VDD, and all I/O pins are 5 V tolerant - meaning they may be safely pulled up to or driven by 5.5 V logic without damage. This allows direct interfacing with legacy 5 V peripherals while maintaining low-voltage core operation for power efficiency.
P89LPC916FDH,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 14
- Program Memory Size:
- 2KB (2K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 4x8b; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC916FDH,118 FAQ
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All P89LPC916FDH,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC916FDH,118 meets industry standards.
7.What is the process for return or replacement of P89LPC916FDH,118?
All P89LPC916FDH,118 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC916FDH,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC916FDH,118 part is unused and in its original packaging.
Return procedure for P89LPC916FDH,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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