My Inquiry
My Account
NXP Semiconductors P89LPC917FDH,129
- Part No.:
- P89LPC917FDH,129
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
P89LPC917FDH,129.pdf
- Description:
- IC MCU 8BIT 2KB FLASH 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,188
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
P89LPC917FDH,129 from NXP Semiconductors is an 8-bit accelerated two-clock 80C51 microcontroller in a 16-pin TSSOP package, featuring 2 kB flash code memory, 256-byte RAM, dual 16-bit timers (including Timer 1), 4-channel 8-bit ADC with DAC output, and 7 keypad interrupt inputs. It operates from 2.4 V to 3.6 V with 5 V-tolerant I/O and supports real-time clock functionality via its 23-bit system timer - deployed in low-cost industrial control panels requiring integrated analog sensing and keypad interface.
For engineers reviewing the P89LPC917FDH,129 datasheet, P89LPC917FDH,129 pinout, P89LPC917FDH,129 application, or P89LPC917FDH,129 equivalent, key selection criteria include Timer 1 availability, CLKOUT capability on P0.7, comparator 2 output (CMP2), INT1 support, and full 7-keypad interrupt mapping - all confirmed for this specific TSSOP16 variant.
Technical Context
The P89LPC917FDH,129 implements an enhanced 80C51 core executing instructions in two to four clocks - delivering six times the throughput of standard 80C51 at the same 18 MHz clock frequency. Its architecture integrates dedicated peripherals including a fractional baud rate UART, dual analog comparators (CMP1/CMP2), and programmable port configurations (quasi-bidirectional, open-drain, push-pull).
It features In-Application Programming (IAP-Lite) with byte-erasable flash sectors, enabling non-volatile data storage within code memory. The device includes a separate on-chip watchdog oscillator, brownout detection with interrupt option, and three power modes (Idle, Power-down, Total Power-down) achieving 1 µA typical current in deep sleep with voltage comparators disabled.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Accelerated two-clock 80C51 CPU; executes all instructions in 2–4 clocks (111–222 ns @ 18 MHz), 6× performance vs. standard 80C51. |
| Flash Memory | 2 kB byte-erasable flash organized in 256-byte sectors; supports IAP-Lite and use as non-volatile data storage. |
| RAM | 256-byte on-chip RAM for data and stack operations; no external memory interface required. |
| Analog Peripherals | 4-input multiplexed 8-bit ADC + single DAC output; two analog comparators with selectable reference (CMPREF). |
| Timers & Clock | Two 16-bit counter/timers (T0, T1); 23-bit system timer usable as RTC; internal RC oscillator calibrated to ±1% with fine tuning. |
| I/O & Interfaces | Up to 14 configurable I/O pins; UART with fractional baud generator; I²C (SCL/SDA); 7 keypad interrupt inputs (KBI0–KBI7); CLKOUT on P0.7. |
| Supply & Robustness | 2.4 V to 3.6 V VDD operation; all I/O pins 5 V tolerant (up to 5.5 V); brownout detect with interrupt option; -40 °C to +85 °C operating range. |
Pinout & Package
Package: TSSOP16 (plastic thin shrink small outline package; 16 leads; body width 4.4 mm; SOT403-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0/CMP2/KBI0 | Port 0 bit 0 / Comparator 2 output / Keypad input 0 | Dedicated CMP2 signal output; enables zero-crossing or threshold detection; KBI0 supports wake-up from power-down on state change. |
| P0.1/CIN2B/KBI1/AD10 | Port 0 bit 1 / CMP2 positive input B / Keypad input 1 / ADC channel 0 | Configurable analog input for comparator or ADC; KBI1 provides hardware-accelerated keypad scanning without CPU polling. |
| P0.2/CIN2A/KBI2/AD11 | Port 0 bit 2 / CMP2 positive input A / Keypad input 2 / ADC channel 1 | Second analog input for differential CMP2 operation; also serves as independent ADC channel for sensor signal digitization. |
| P0.3/CIN1B/KBI3/AD12 | Port 0 bit 3 / CMP1 positive input B / Keypad input 3 / ADC channel 2 | Supports dual comparator configuration; KBI3 enables matrix keypad row/column decoding with automatic interrupt generation. |
| P0.4/CIN1A/KBI4/AD13/DAC1 | Port 0 bit 4 / CMP1 positive input A / Keypad input 4 / ADC channel 3 / DAC output | Single-pin DAC1 output allows analog waveform generation or bias voltage setting; shared with ADC input for bidirectional analog control. |
| P0.5/CMPREF/KBI5/CLKIN | Port 0 bit 5 / Comparator reference input / Keypad input 5 / External clock input | CMPREF sets common-mode or threshold voltage for both comparators; CLKIN accepts external timing source up to 18 MHz. |
| P0.7/T1/KBI7/CLKOUT | Port 0 bit 7 / Timer 1 I/O / Keypad input 7 / Clock output | Unique to P89LPC917: enables T1 overflow toggling, external event counting, or buffered system clock distribution (CLKOUT). |
| P1.0/TXD | Port 1 bit 0 / UART transmit output | Drives serial data output with slew-rate control (~10 ns ramp time) to reduce EMI; compatible with RS-232 level shifters. |
| P1.1/RXD | Port 1 bit 1 / UART receive input | Schmitt-triggered RXD input ensures noise immunity on asynchronous serial lines; supports framing error and break detection. |
| P1.2/T0/SCL | Port 1 bit 2 / Timer 0 I/O / I²C clock line | Open-drain configuration when used as SCL; supports standard-mode I²C (100 kHz); T0 overflow can toggle P1.2 for PWM-like output. |
| P1.3/INT0/SDA | Port 1 bit 3 / External interrupt 0 / I²C data line | Open-drain SDA with internal pull-up option; INT0 triggers high-priority interrupt on falling edge for fast response to critical events. |
| P1.4/INT1 | Port 1 bit 4 / External interrupt 1 input | Dedicated edge-sensitive interrupt input; supports four priority levels; used for emergency stop, fault signaling, or sensor alerts. |
| P1.5/RST | Port 1 bit 5 / Reset input | Active-low reset pin; must be enabled for >12 MHz operation; used to force ISP mode during power-on sequence. |
| VSS | Ground reference (pin 4) | 0 V reference for analog and digital domains; decoupling capacitor placement near this pin minimizes noise coupling. |
| VDD | Power supply (pin 12) | 2.4–3.6 V supply for core and I/O; internal voltage regulator ensures stable operation across full temperature range. |
Key Features
| Feature | Design Value |
|---|---|
| Accelerated 2-clock 80C51 core | Enables 18 MHz operation with 111 ns instruction cycle - reduces EMI and power consumption versus standard 80C51 at equivalent performance. |
| Byte-erasable flash memory | Allows individual bytes to serve as EEPROM-like non-volatile storage without sector-level erase overhead - ideal for calibration data logging. |
| 7-keypad interrupt inputs (KBI0–KBI7) | Hardware-accelerated scan logic eliminates CPU polling; supports up to 7 independent mechanical or capacitive keys with wake-up-from-sleep capability. |
| Comparator 2 output (CMP2) and reference (CMPREF) | Provides rail-to-rail analog comparison with user-selectable hysteresis; CMPREF enables precise threshold setting for overvoltage/undervoltage monitoring. |
| CLKOUT on P0.7 | Delivers buffered system clock (divided or undivided) to external logic or test equipment - simplifies timing validation and synchronization. |
| 5 V-tolerant I/O pins | Eliminates level-shifting components when interfacing with legacy 5 V peripherals or sensors - reduces BOM cost and board area. |
Applications
| Industrial Control Panel | Smart Sensor Node |
|---|---|
|
Use Scenario: Compact front-panel controller with membrane keypad, LED indicators, and analog sensor inputs for HVAC or pump monitoring. IC Role / Device Role / Timing Role: Central MCU managing keypad scan, ADC sampling of temperature/humidity, DAC-based actuator bias, and UART telemetry to host PLC. Use Value: Integrated 7-keypad interrupt and dual comparators enable responsive UI and real-time fault detection without external glue logic. |
Use Scenario: Battery-powered environmental sensor node measuring light, pressure, and supply voltage with local alarm triggering. IC Role / Device Role / Timing Role: Low-power system controller using Total Power-down mode (1 µA), wake-up on KBI or ADC threshold crossing, and RTC-stamped data logging. Use Value: On-chip brownout detect + interrupt and 23-bit system timer allow graceful shutdown and time-synchronized event capture without external components. |
| LED Lighting Controller | Embedded Power Monitor |
|
Use Scenario: Dimmable LED driver with thermal foldback, overcurrent protection, and brightness adjustment via rotary encoder or buttons. IC Role / Device Role / Timing Role: Real-time PWM generation via Timer 0 overflow toggle, analog comparator-based current sensing, and DAC-controlled reference voltage. Use Value: T1 on P0.7 supports synchronized multi-channel dimming; 5 V-tolerant I/O interfaces directly with encoder outputs and MOSFET gate drivers. |
Use Scenario: AC/DC adapter or PoE-powered device monitoring input voltage, load current, and thermal margin with alert signaling. IC Role / Device Role / Timing Role: Analog comparator pair (CMP1/CMP2) monitors VIN and VSENSE; UART reports status; internal RC oscillator ensures timing stability without crystal. Use Value: Factory-calibrated ±1% RC oscillator eliminates crystal cost and layout sensitivity while maintaining sufficient accuracy for power sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC916FDH | Lacks Timer 1, CLKOUT, and CMP2 output; includes SPI interface instead. | Suitable for systems requiring serial peripheral expansion (e.g., display drivers, EEPROMs) but not needing T1-based PWM or clock distribution. | Select P89LPC916FDH only if SPI is required and Timer 1/CLKOUT/CMP2 are unused - pinout differs slightly (P2.2–P2.5 replace P0.7/P1.4 functions). |
| P89LPC915FDH | 14-pin TSSOP; lacks Timer 1, CLKOUT, SPI, and P2 port; supports only 6 keypad interrupts. | Better suited for ultra-compact designs with minimal I/O count and no need for secondary timer or clock output. | Choose P89LPC915FDH for space-constrained applications where 6-keypad support suffices and P0.7/INT1 are unnecessary - not pin-compatible with P89LPC917FDH. |
Compared with P89LPC916FDH and P89LPC915FDH, the P89LPC917FDH uniquely delivers Timer 1, CLKOUT, and CMP2 output in a 16-pin TSSOP - making it optimal for designs requiring precise timing coordination, external clock distribution, or dual-comparator fault monitoring without adding discrete components.
Availability
P89LPC917FDH,129 is available at Aetrix Electronics and suitable for industrial control panels, smart sensor nodes, LED lighting controllers, and embedded power monitors requiring stable component supply, long-term lifecycle support, and verified 5 V-tolerant I/O operation.
Supply support for P89LPC917FDH,129 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC917FDH,129 belongs to NXP's LPC900 family of 8-bit microcontrollers designed for cost-sensitive, space-constrained embedded systems requiring integrated analog peripherals, low-power operation, and robust I/O flexibility.
FAQ
What is the maximum operating frequency of the P89LPC917FDH,129?
The P89LPC917FDH,129 supports a maximum CPU clock frequency of 18 MHz. At this speed, its accelerated two-clock 80C51 core achieves instruction cycle times of 111 ns to 222 ns - six times faster than a standard 80C51 running at the same frequency. The internal RC oscillator is factory-calibrated to ±1% and can be fine-tuned, or an external crystal/clock source may be applied via CLKIN (P0.5).
Does the P89LPC917FDH,129 support in-application programming (IAP)?
Yes, the P89LPC917FDH,129 supports In-Application Programming (IAP-Lite) with byte-erasable flash memory. This allows firmware updates or parameter storage during normal operation without requiring a full chip erase. Code memory sectors (256-byte) and pages (16-byte) can be individually erased and reprogrammed, enabling use of flash for non-volatile data storage such as calibration values or device configuration.
What are the key differentiating features of the P89LPC917FDH,129 versus P89LPC916FDH?
The P89LPC917FDH,129 includes Timer 1, CLKOUT on P0.7, and Comparator 2 output (CMP2) - features absent in the P89LPC916FDH. In exchange, P89LPC916FDH adds an SPI interface and omits CMP2 and T1. Both share the same TSSOP16 package, but pin functions differ: P0.7 on P89LPC917FDH is multifunctional (T1/KBI7/CLKOUT), whereas P89LPC916FDH uses P2.2–P2.5 for SPI signals.
Can the P89LPC917FDH,129 operate without an external crystal?
Yes, the P89LPC917FDH,129 can operate using its internal RC oscillator, which is factory-calibrated to ±1% accuracy and supports fine tuning via software. This eliminates the need for external crystal or resonator components, reducing BOM cost and PCB area - ideal for cost-sensitive and space-constrained applications where moderate timing precision is acceptable.
How many keypad interrupt inputs does the P89LPC917FDH,129 support?
The P89LPC917FDH,129 supports seven (7) dedicated keypad interrupt inputs: KBI0 through KBI5 on Port 0, plus KBI7 on P0.7. This hardware-accelerated feature enables immediate CPU wake-up and interrupt generation upon key press/release without software polling - significantly improving responsiveness and reducing active power consumption in human-interface applications.
P89LPC917FDH,129 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, UART/USART
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 14
- Program Memory Size:
- 2KB (2K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 4x8b; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
P89LPC917FDH,129 FAQ
1.How can I place an order for P89LPC917FDH,129 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC917FDH,129 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P89LPC917FDH,129 reliable?
The price and inventory of P89LPC917FDH,129 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P89LPC917FDH,129 is usually 5 days.
3.What payment methods are accepted for P89LPC917FDH,129?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P89LPC917FDH,129 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P89LPC917FDH,129?
P89LPC917FDH,129 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P89LPC917FDH,129 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P89LPC917FDH,129?
For technical support, including P89LPC917FDH,129 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC917FDH,129 requirements.
6.How does Aetrix verify that P89LPC917FDH,129 is sourced from the original manufacturer or authorized distributors?
All P89LPC917FDH,129 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC917FDH,129 meets industry standards.
7.What is the process for return or replacement of P89LPC917FDH,129?
All P89LPC917FDH,129 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC917FDH,129, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC917FDH,129 part is unused and in its original packaging.
Return procedure for P89LPC917FDH,129:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
P89LPC917FDH,129 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
