NXP Semiconductors P89LPC921FN,112
- Part No.:
- P89LPC921FN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
P89LPC921FN,112.pdf
- Description:
- IC MCU 8BIT 4KB FLASH 20DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
P89LPC921FN,112 from NXP Semiconductors (formerly Philips) is a 4 kB Flash, 256-byte RAM, 8-bit microcontroller based on an accelerated two-clock 80C51 core operating up to 18 MHz, featuring dual 16-bit timers, real-time clock, two analog comparators, and I²C/UART peripherals - deployed in industrial control panels requiring low-power, high-integration embedded logic with minimal external components.
For engineers reviewing the P89LPC921FN,112 datasheet, P89LPC921FN,112 pinout, P89LPC921FN,112 application, or P89LPC921FN,112 equivalent, this page delivers verified technical context, package-validated pin functions, real-world use cases, and confirmed alternative options for legacy 8051-based designs where Flash size, I/O flexibility, and 3 V operation are critical selection criteria.
Technical Context
The P89LPC921FN,112 executes instructions in two to four CPU clocks - six times faster than standard 80C51 at identical frequencies - using a configurable oscillator that supports internal RC (7.373 MHz ±1%), external crystal (20 kHz–18 MHz), or watchdog (400 kHz) sources. Its CCLK is derived from OSCCLK via a programmable DIVM register, and PCLK (peripheral clock) runs at CCLK/2.
It integrates dual 16-bit counter/timers (T0/T1), each configurable as PWM outputs or port toggle triggers; a real-time clock usable as system timer; two analog comparators with selectable inputs and reference; and an enhanced UART with fractional baud rate generation, break detection, and automatic address recognition - all operating across 2.4 V–3.6 V with 5 V-tolerant I/O pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Two-clock 80C51 CPU executing most instructions in 2–4 CCLK cycles; 6× performance vs. standard 80C51 at same frequency. |
| Flash Memory | 4 kB on-chip Flash with 1 kB erasable sectors and 64-byte page erase; supports in-application programming (IAP) and serial flash programming. |
| RAM | 256-byte on-chip data RAM; no external memory interface required for typical embedded control tasks. |
| Operating Voltage | 2.4 V to 3.6 V VDD; I/O pins tolerate up to 5.5 V - enables direct interfacing with 5 V logic without level shifters. |
| Max Clock Frequency | 18 MHz CPU clock (CCLK); supports crystal, RC, watchdog, or external clock input with user-selectable oscillator configuration bits. |
| Peripherals | Dual 16-bit timers (T0/T1), real-time clock/system timer, two analog comparators, enhanced UART, 400 kHz I²C bus, keypad interrupt (8 inputs), watchdog timer with independent oscillator. |
| Power Modes | Idle mode and two Power-down modes; typical Power-down current is 1 µA (with voltage comparators disabled). |
Pinout & Package
Package: DIP20 (plastic dual in-line package, 20 leads, 300 mil width; SOT146-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - KBI0/CMP2/P0.0 | Port 0 bit 0 / Comparator 2 output / Keypad input 0 | Configurable I/O with Schmitt trigger; supports keyboard scan and analog comparison simultaneously. |
| 2 - P1.7 | Port 1 bit 7 | High-current source (20 mA) capable; used for LED drive or direct relay control without external drivers. |
| 3 - P1.6 | Port 1 bit 6 | High-current source (20 mA); supports active-low reset signaling or sensor interface with pull-up. |
| 4 - RST/P1.5 | Reset input / Port 1 bit 5 | Input-only pin; externally asserted active-low reset; must be enabled via Flash config for >12 MHz operation. |
| 5 - VSS | Ground reference | 0 V return path for all internal circuits and I/O; requires low-impedance connection to minimize noise coupling. |
| 6 - XTAL1/P3.1 | Oscillator input / Port 3 bit 1 | Crystal/resonator input or external clock source; functions as GPIO only when internal RC or watchdog oscillator selected. |
| 7 - CLKOUT/XTAL2/P3.0 | Oscillator output / Clock divider output | Provides CCLK/2 clock signal to external devices when crystal not used; enabled via TRIM register ENCLK bit. |
| 8 - INT1/P1.4 | External interrupt 1 / Port 1 bit 4 | High-current source (20 mA); supports edge-triggered wake-up from Power-down mode. |
| 9 - SDA/INT0/P1.3 | I²C data / External interrupt 0 / Port 1 bit 3 | Open-drain I/O; supports bidirectional I²C communication and asynchronous interrupt triggering. |
| 10 - SCL/T0/P1.2 | I²C clock / Timer 0 input / Port 1 bit 2 | Open-drain I/O; provides synchronous clock for I²C bus and external event counting for T0. |
| 11 - P0.1/CIN2B/KBI1 | Port 0 bit 1 / Comparator 2 positive input B / Keypad input 1 | Multi-function analog/digital pin; enables differential comparator operation and matrix key scanning. |
| 12 - P0.2/CIN2A/KBI2 | Port 0 bit 2 / Comparator 2 positive input A / Keypad input 2 | Supports dual comparator configurations and simultaneous keypad polling without additional hardware. |
| 13 - P0.3/CIN1B/KBI3 | Port 0 bit 3 / Comparator 1 positive input B / Keypad input 3 | Enables threshold-based sensing (e.g., battery voltage monitoring) alongside keyboard matrix decoding. |
| 14 - P0.4/CIN1A/KBI4 | Port 0 bit 4 / Comparator 1 positive input A / Keypad input 4 | Allows independent reference selection per comparator; supports multi-level analog event detection. |
| 15 - VDD | Power supply | Primary 2.4–3.6 V supply rail; powers core, peripherals, and I/O; decoupling capacitor required near pin. |
| 16 - P0.5/CMPREF/KBI5 | Port 0 bit 5 / Comparator reference (negative) input / Keypad input 5 | Shared reference node for both comparators; enables ratiometric or fixed-threshold comparisons. |
| 17 - P0.6/CMP1/KBI6 | Port 0 bit 6 / Comparator 1 output / Keypad input 6 | Comparator output directly drives port latch; eliminates need for external op-amp or comparator IC. |
| 18 - P0.7/T1/KBI7 | Port 0 bit 7 / Timer 1 external count input / Keypad input 7 | Supports pulse counting (e.g., flow meter) while maintaining full keypad interrupt capability. |
| 19 - P1.0/TXD | Port 1 bit 0 / UART transmit output | Push-pull or open-drain configurable; drives RS-232 level shifter or TTL serial interface directly. |
| 20 - P1.1/RXD | Port 1 bit 1 / UART receive input | Schmitt-triggered input; tolerates slow-rising signals and noise; compatible with 3.3 V or 5 V logic levels. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable port output modes | Each I/O pin supports quasi-bidirectional, open-drain, push-pull, or input-only - enabling direct LED drive, I²C bus termination, and robust sensor interfacing. |
| On-chip RC oscillator (7.373 MHz ±1%) | Factory-calibrated oscillator eliminates external crystal and load capacitors - reduces BOM cost and PCB area in cost-sensitive applications. |
| Programmable port pattern match interrupt | Port 0 generates interrupt when pin values match or mismatch a user-defined 8-bit pattern - enables efficient wake-up from Power-down on specific button combinations. |
| Controlled slew rate outputs | ~10 ns minimum ramp time on all outputs - reduces EMI emissions and improves signal integrity in mixed-signal environments. |
| Four interrupt priority levels | Hardware-enforced priority arbitration allows deterministic response to time-critical events (e.g., fault detection) without software overhead. |
| Flash security bits | Prevents unauthorized read-out of firmware during in-circuit programming - protects proprietary algorithms in production units. |
Applications
| Industrial Control Panel | Smart Sensor Node |
|---|---|
Use Scenario: Standalone panel with keypad, LCD, and relay outputs managing HVAC setpoints and status feedback. IC Role / Device Role / Timing Role: Central controller executing state machine logic, scanning 8-key matrix, driving 20 mA LEDs, and generating PWM for fan speed control. Use Value: Eliminates external oscillator, level shifters, and discrete comparators - reduces component count by ≥7 parts versus standard 8051 design. |
Use Scenario: Battery-powered environmental monitor measuring temperature, humidity, and supply voltage with periodic wireless reporting. IC Role / Device Role / Timing Role: Low-power system manager using Power-down mode between readings, real-time clock for scheduling, and analog comparators for brownout detection. Use Value: Achieves 1 µA typical Power-down current with comparators disabled - extends CR2032 battery life beyond 5 years in sleep-dominated operation. |
| Legacy Equipment Upgrade | Embedded Power Supply Monitor |
Use Scenario: Retrofitting aging 8051-based test equipment with enhanced firmware and communication capability without board redesign. IC Role / Device Role / Timing Role: Drop-in replacement for P89C51RD2 with identical DIP20 footprint, supporting in-system Flash reprogramming via UART. Use Value: Maintains existing PCB layout while adding I²C peripheral support and fractional baud rate generation for modern host interfaces. |
Use Scenario: Monitoring 3.3 V and 5 V rails in telecom power modules with overvoltage/undervoltage alarms and fault logging. IC Role / Device Role / Timing Role: Dual-comparator supervisor with programmable thresholds, non-volatile fault timestamping via real-time clock, and UART alert transmission. Use Value: Replaces discrete voltage monitor ICs and EEPROM-based logging - consolidates supervision and data retention into single chip. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT89LP51RC2-20PU | 4 kB Flash, 256-byte RAM, 20 MHz max, 2.4–5.5 V operation; no on-chip RC oscillator or analog comparators. | Lacks integrated comparators and real-time clock; requires external crystal and reset circuitry. | Choose when higher clock margin (20 MHz) is needed and analog supervision is handled externally. |
| STC89C52RC-PDIP40 | 8 kB Flash, 512-byte RAM, 5 V only, 0–80 MHz operation; no I²C, no RTC, no programmable slew rate. | Requires 5 V supply and external crystal; lacks low-voltage operation and EMI-reduction features. | Choose for high-speed 5 V systems where Flash size is primary constraint and power efficiency is secondary. |
Compared with AT89LP51RC2-20PU and STC89C52RC-PDIP40, the P89LPC921FN,112 delivers integrated analog supervision, 3 V operation with 5 V-tolerant I/O, and factory-trimmed RC oscillator - reducing external component count and simplifying power architecture in space-constrained industrial designs.
Availability
P89LPC921FN,112 is available at Aetrix Electronics and suitable for industrial control panels, smart sensor nodes, legacy equipment upgrades, and embedded power supply monitors requiring stable component supply, long-term lifecycle support, and drop-in compatibility with existing DIP20 layouts.
Supply support for P89LPC921FN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (originally Philips Semiconductors) is a global leader in high-performance mixed-signal ICs, with deep expertise in automotive, industrial, and secure connectivity solutions.
The P89LPC921FN,112 belongs to the LPC900 family - designed specifically for cost-sensitive, low-power 8051-based embedded control applications where integration of Flash, analog peripherals, and flexible clocking reduces system complexity and bill-of-materials cost.
FAQ
What is the Flash memory capacity of the P89LPC921FN,112?
The P89LPC921FN,112 contains 4 kB of on-chip Flash memory organized in 1 kB erasable sectors with 64-byte page erase granularity. This capacity supports moderate firmware complexity while enabling in-application programming (IAP) for field updates without removing the P89LPC921FN,112 from the target system.
Does the P89LPC921FN,112 support 5 V logic interfacing?
Yes, the P89LPC921FN,112 features 5 V-tolerant I/O pins - all port pins may be pulled up to or driven by 5.5 V signals while operating from a 2.4–3.6 V VDD supply. This eliminates level-shifting components when interfacing with legacy 5 V peripherals, simplifying design around the P89LPC921FN,112.
Can the P89LPC921FN,112 operate without an external crystal?
Yes, the P89LPC921FN,112 includes a factory-calibrated 7.373 MHz ±1% on-chip RC oscillator, configurable via Flash configuration bits. When selected, this oscillator allows full operation with only VDD, VSS, and optional reset - no external crystal or capacitors required for the P89LPC921FN,112.
What are the power consumption characteristics of the P89LPC921FN,112 in low-power modes?
The P89LPC921FN,112 offers Idle and two Power-down modes. Typical Power-down current is 1 µA when voltage comparators are disabled - verified under 3.0 V, 25 °C conditions. Wake-up from Power-down is triggered by low-level interrupts on designated pins, enabling rapid response to external events while minimizing average current draw for the P89LPC921FN,112.
How many analog comparators does the P89LPC921FN,112 integrate, and what are their key capabilities?
The P89LPC921FN,112 integrates two independent analog comparators (CMP1 and CMP2) with selectable positive inputs (CIN1A/CIN1B, CIN2A/CIN2B), shared negative reference input (CMPREF), and dedicated output pins (CMP1, CMP2). Each comparator supports hysteresis and can generate interrupts - enabling threshold detection, battery monitoring, and overvoltage protection without external components for the P89LPC921FN,112.
P89LPC921FN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, UART/USART
- Peripherals:
- Brown-out Detect/Reset, LED, POR, PWM, WDT
- Number of I/O:
- 18
- Program Memory Size:
- 4KB (4K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P89LPC921FN,112 FAQ
1.How can I place an order for P89LPC921FN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC921FN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P89LPC921FN,112 reliable?
The price and inventory of P89LPC921FN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P89LPC921FN,112 is usually 5 days.
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5.How can I obtain technical support or documentation for P89LPC921FN,112?
For technical support, including P89LPC921FN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC921FN,112 requirements.
6.How does Aetrix verify that P89LPC921FN,112 is sourced from the original manufacturer or authorized distributors?
All P89LPC921FN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC921FN,112 meets industry standards.
7.What is the process for return or replacement of P89LPC921FN,112?
All P89LPC921FN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC921FN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC921FN,112 part is unused and in its original packaging.
Return procedure for P89LPC921FN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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