NXP Semiconductors P89LPC9321FN,112
- Part No.:
- P89LPC9321FN,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
P89LPC9321FN,112.pdf
- Description:
- IC MCU 8BIT 8KB FLASH 28DIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,835
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
P89LPC9321FN,112 from NXP Semiconductors is an 8-bit accelerated two-clock 80C51 microcontroller in a 28-pin DIP package, featuring 8 kB byte-erasable flash, 512-byte on-chip data EEPROM, dual analog comparators with PGA, and 23 I/O pins. It operates from 2.4 V to 3.6 V with 5 V-tolerant I/Os and supports real-time clock, PWM, capture/compare, UART, I²C, and SPI-ideal for industrial control panels requiring compact, low-power embedded logic with analog sensing.
For engineers reviewing the P89LPC9321FN,112 datasheet, P89LPC9321FN,112 pinout, P89LPC9321FN,112 application, or P89LPC9321FN,112 equivalent, this page delivers verified technical context, validated pin functions, confirmed peripheral capabilities (including CCU, RTC, and programmable oscillator), and precise alternative part guidance for production design-in and legacy replacement.
Technical Context
The P89LPC9321FN,112 executes instructions in 2–4 clocks-six times faster than standard 80C51 at same frequency-enabling 111 ns minimum instruction cycle at 18 MHz. Its architecture integrates a 23-bit system timer (7-bit prescaler + 16-bit counter) usable as real-time clock, plus a Capture/Compare Unit supporting PWM generation, input capture, and output compare with four independent channels (OCA–OCD, ICA–ICB).
It embeds dual analog comparators with selectable inputs and reference, a single programmable gain amplifier (2×/4×/8×/16×), and configurable port outputs (quasi-bidirectional, open-drain, push-pull). Power management includes idle mode, two power-down modes (1 μA typical), brownout detect (4-level), and on-chip oscillators (RC, watchdog, external) with dynamic switching for performance/power trade-offs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Accelerated two-clock 80C51 CPU; 6× performance vs. standard 80C51 at same frequency |
| Flash Memory | 8 kB byte-erasable flash organized in 1 kB sectors and 64-byte pages; enables non-volatile data storage via single-byte erase |
| Data Storage | 512-byte on-chip customer data EEPROM for device serialization and setup parameter retention |
| Analog Peripherals | Dual analog comparators with selectable inputs/reference; integrated PGA with gains of 2×, 4×, 8×, or 16× |
| Timers & RTC | Two 16-bit counter/timers + 23-bit system timer (7-bit prescaler + 16-bit counter); configurable as real-time clock |
| Communication Interfaces | Enhanced UART (fractional baud rate, break detect), 400 kHz I²C-bus, and SPI ports |
| Operating Voltage | 2.4 V to 3.6 V VDD; all I/O pins 5 V tolerant (up to 5.5 V), enabling direct interface with 5 V logic without level shifters |
Pinout & Package
Package: 28-pin plastic dual in-line package (DIP28), 600 mil width, through-hole mounting compatible with legacy PCB layouts and manual prototyping.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0.0/CMP2/KBI0 | Port 0 bit 0 / Comparator 2 output / Keypad interrupt 0 | Configurable I/O with Schmitt trigger; supports analog comparator output and keyboard scan input |
| P1.5/RST | Port 1 bit 5 / External reset input | Input-only pin; LOW assertion triggers hardware reset and forces ISP mode during power-on sequence |
| P2.6/OCA | Port 2 bit 6 / Output Compare A | Hardware-generated PWM or timing waveform output driven by Capture/Compare Unit channel A |
| P3.0/XTAL2/CLKOUT | Port 3 bit 0 / Crystal oscillator output / CPU clock divided-by-2 | Outputs crystal drive signal when XTAL mode selected; alternatively provides CLKOUT (CPU clock/2) for system synchronization |
| VDD | Power supply | Primary 2.4–3.6 V supply for core and I/O; powers all peripherals including analog comparators and EEPROM |
| VSS | Ground reference | 0 V return path for all internal circuits; must be low-impedance connection for stable analog and digital operation |
Key Features
| Feature | Design Value |
|---|---|
| In-Application Programming (IAP) | Enables firmware updates while running-critical for field-upgradable industrial controllers without device removal |
| Programmable Port Output Types | Per-pin configuration (quasi-bidirectional, open-drain, push-pull, input-only) optimizes drive strength and noise immunity per peripheral interface |
| Port Input Pattern Match Detect | Port 0 generates interrupt when pin states match programmable 8-bit pattern-reduces CPU polling overhead in keypad or status monitoring |
| Controlled Slew Rate Outputs | ~10 ns minimum ramp time on all outputs suppresses EMI in noise-sensitive environments like medical or test equipment |
| Four Interrupt Priority Levels | Supports deterministic real-time response for mixed-criticality tasks (e.g., fault detection > sensor read > UI update) |
Applications
| Industrial Control Panel | Smart Sensor Node |
|---|---|
Use Scenario: Standalone HMI panel with keypad, LED indicators, and analog sensor inputs for HVAC zone control. IC Role / Device Role / Timing Role: Central controller executing real-time logic, driving LEDs via high-current I/O (20 mA sourcing on P0.3–P0.7), reading analog thresholds via comparators, and managing serial comms to central gateway. Use Value: Integrated 512-byte EEPROM stores calibration offsets and user preferences; CCU generates precise PWM for fan speed control without external timers. | Use Scenario: Battery-powered environmental monitor measuring temperature/humidity with wake-on-event capability. IC Role / Device Role / Timing Role: Low-power sensor aggregator using power-down mode (1 μA), waking on keypad or comparator threshold breach, then sampling sensors and transmitting via UART/I²C. Use Value: On-chip RC oscillator eliminates external crystal, reducing BOM cost and board space; brownout detect ensures graceful shutdown before data corruption. |
| Legacy Equipment Retrofit | Programmable Logic Module |
Use Scenario: Replacement for obsolete 8051-based motor controller in factory automation systems. IC Role / Device Role / Timing Role: Pin-compatible upgrade path (DIP28 footprint) retaining existing PCB layout while adding enhanced UART, I²C, and analog front-end for added diagnostics. Use Value: Same 28-pin DIP package and 80C51 instruction set ensure drop-in software compatibility; flash security bits prevent IP leakage in deployed units. | Use Scenario: Configurable logic block in test fixtures, implementing custom state machines for signal routing and protocol translation. IC Role / Device Role / Timing Role: Programmable sequencer using CCU for precise timing events, UART for host command parsing, and port pattern matching for stimulus detection. Use Value: In-System Programming (ISP) allows reconfiguration in final assembly; auxiliary 512-byte RAM buffers protocol data without external SRAM. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P89LPC9351FN,112 | Same core and package, but with 16 kB flash, 1 kB EEPROM, and additional 8-bit A/D converter | Required when higher code density or ADC-based analog acquisition is needed beyond comparator-only sensing | Select if future firmware expansion or analog measurement resolution beyond comparator thresholds is anticipated |
| P89LPC9251FN,112 | Same family, 28-pin DIP, but with 4 kB flash, no data EEPROM, and only one analog comparator | Suitable for simpler control tasks where EEPROM persistence and dual-comparator redundancy are unnecessary | Choose for cost-sensitive designs with minimal firmware and no need for serialized device data storage |
Compared with P89LPC9321FN,112, the P89LPC9351FN,112 adds ADC and memory headroom for feature-rich upgrades, while the P89LPC9251FN,112 reduces cost and complexity for basic logic-only implementations-both maintain identical DIP28 footprint and 80C51 compatibility.
Availability
P89LPC9321FN,112 is available at Aetrix Electronics and suitable for industrial control panels, smart sensor nodes, legacy equipment retrofits, and programmable logic modules requiring stable component supply across extended product lifecycles.
Supply support for P89LPC9321FN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The P89LPC9321FN,112 belongs to NXP's LPC900 family of enhanced 80C51 microcontrollers, designed specifically for cost-sensitive, space-constrained embedded systems needing integrated analog peripherals, low-power operation, and robust in-system programmability.
FAQ
What is the maximum operating frequency of the P89LPC9321FN,112?
The P89LPC9321FN,112 supports a maximum operating frequency of 18 MHz, achievable using the internal RC oscillator (with optional clock doubler), external crystal/resonator, or watchdog oscillator. At 18 MHz, its accelerated two-clock architecture delivers instruction cycle times of 111 ns to 222 ns-six times faster than a standard 80C51 at the same clock rate. The P89LPC9321FN,112 maintains full functionality across its 0–18 MHz range.
Does the P89LPC9321FN,112 support in-system programming (ISP)?
Yes, the P89LPC9321FN,112 supports In-System Programming (ISP) via its UART interface, allowing firmware updates while the device remains soldered in the target application. This capability eliminates the need for socketed programming and enables field upgrades. The P89LPC9321FN,112 also supports In-Circuit Programming (ICP) and In-Application Programming (IAP), with flash security bits preventing unauthorized readout of protected code.
How many I/O pins does the P89LPC9321FN,112 provide, and what are their voltage tolerances?
The P89LPC9321FN,112 provides 23 I/O pins minimum and up to 26 I/O pins depending on oscillator and reset configuration. All I/O pins are 5 V tolerant-capable of being pulled up to or driven to 5.5 V-even when VDD is operated at 2.4 V to 3.6 V. This eliminates external level-shifting components when interfacing with legacy 5 V peripherals or logic families.
What analog peripherals are integrated into the P89LPC9321FN,112?
The P89LPC9321FN,112 integrates two analog comparators (CMP1 and CMP2) with selectable positive/negative inputs and reference sources, plus a single Programmable Gain Amplifier (PGA) offering gains of 2×, 4×, 8×, or 16× that can be applied to comparator inputs. These features enable precision threshold detection, battery monitoring, and simple analog signal conditioning without external op-amps or ADCs-directly supported in the P89LPC9321FN,112's hardware architecture.
Is the P89LPC9321FN,112 pin-compatible with other members of the LPC900 family?
The P89LPC9321FN,112 shares the same 28-pin DIP package and core pinout with other LPC900 variants like P89LPC9351FN,112 and P89LPC9251FN,112, but functional pin assignments (e.g., peripheral multiplexing) differ based on feature set. While mechanical footprint is identical, electrical and firmware compatibility requires verification against each variant's datasheet-especially for pins assigned to unique peripherals such as the ADC in the P89LPC9351FN,112. The P89LPC9321FN,112 is not a drop-in replacement for parts with differing peripheral configurations.
P89LPC9321FN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Series:
- LPC900
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 18MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 26
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 512 x 8
- RAM Size:
- 768 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
P89LPC9321FN,112 FAQ
1.How can I place an order for P89LPC9321FN,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for P89LPC9321FN,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P89LPC9321FN,112 reliable?
The price and inventory of P89LPC9321FN,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P89LPC9321FN,112 is usually 5 days.
3.What payment methods are accepted for P89LPC9321FN,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P89LPC9321FN,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P89LPC9321FN,112?
P89LPC9321FN,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P89LPC9321FN,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P89LPC9321FN,112?
For technical support, including P89LPC9321FN,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P89LPC9321FN,112 requirements.
6.How does Aetrix verify that P89LPC9321FN,112 is sourced from the original manufacturer or authorized distributors?
All P89LPC9321FN,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P89LPC9321FN,112 meets industry standards.
7.What is the process for return or replacement of P89LPC9321FN,112?
All P89LPC9321FN,112 units undergo pre-shipment inspection (PSI). If there is an issue with P89LPC9321FN,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P89LPC9321FN,112 part is unused and in its original packaging.
Return procedure for P89LPC9321FN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
P89LPC9321FN,112 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

