NXP Semiconductors PCA9509D,112

Overview

PCA9509D,112 from NXP Semiconductors is a bidirectional I²C-bus/SMBus level-translating repeater enabling 1.35 V–1.9 V low-voltage processors to interface with 3.0 V–5.5 V I²C/SMBus peripherals. It provides isolated buffering for SDA and SCL lines, supports arbitration and clock stretching, operates up to 400 kHz, and features lock-up-free current-sensing logic on port A. It is used in mixed-voltage embedded systems such as battery-powered sensor hubs interfacing ultra-low-power microcontrollers with legacy 3.3 V I²C sensors.

For engineers reviewing the PCA9509D,112 datasheet, PCA9509D,112 pinout, PCA9509D,112 application, or PCA9509D,112 equivalent, key selection criteria include its dual-supply voltage translation range (1.35 V–1.9 V on port A, 3.0 V–5.5 V on port B), absence of external pull-ups on port A, EN-controlled enable timing, powered-off high-impedance I/Os, and compatibility with Standard-mode and Fast-mode I²C-bus devices.

Technical Context

The PCA9509D,112 implements asymmetric open-drain buffering: port A uses a 1 mA current-source pull-up and 200 Ω pull-down to achieve ~0.2 V LOW with 50 mV input threshold margin, preventing bus lock-up during contention; port B employs SMBus-compliant 0.3×VCC(B) input thresholds and hard LOW drive (≤0.2 V at 6 mA). Its internal power-up circuit requires VCC(A) > 0.8 V and VCC(B) > 2.5 V before driver activation.

Signal translation is strictly unidirectional per edge: a falling edge on port A below ~0.15 V triggers port B pull-down; a falling edge on port B below 0.3×VCC(B) triggers port A pull-down. Ground offset between port A and device ground must remain ≤50 mV to ensure reliable VILc recognition and avoid false LOW rejection.

Key Specifications

Pinout & Package

PCA9509D,112 is housed in an SO8 package (SOT96-1): plastic small outline, 8 leads, 3.9 mm body width, 1.27 mm lead pitch. Pin 1 = VCC(A); Pin 2 = A1 (port A I/O); Pin 3 = A2 (port A I/O); Pin 4 = GND; Pin 5 = EN (active HIGH enable); Pin 6 = B2 (port B I/O); Pin 7 = B1 (port B I/O); Pin 8 = VCC(B).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-bus level translation applications.

Compared with TCA9517A and PCA9509A, the PCA9509D,112 uniquely balances ultra-low-voltage port A operation (1.35 V minimum), integrated pull-up elimination, and robust lock-up prevention-making it optimal for battery-constrained 1.35 V–1.9 V embedded designs where reliability and BOM simplification are prioritized over sub-1.35 V support.

Availability

PCA9509D,112 is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control modules, medical wearables, and server management controllers requiring stable component supply across extended temperature ranges (−40 °C to +85 °C) and long production lifecycles.

Supply support for PCA9509D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in interface and power management ICs.

The PCA9509 product line was designed specifically to solve mixed-voltage I²C-bus interoperability challenges in resource-constrained embedded systems, emphasizing lock-up immunity, low-power operation, and seamless protocol transparency.

FAQ

What is the minimum operating voltage on port A for PCA9509D,112?

The PCA9509D,112 requires VCC(A) ≥ 1.35 V for guaranteed operation per datasheet specifications. While the device may function down to 0.95 V in some conditions, the VILc (contention input threshold) degrades below 1.35 V, risking unreliable LOW detection and potential bus lock-up. For sub-1.35 V applications, NXP specifies the PCA9509A as the drop-in replacement. Always verify VILc margin using Figure 8 and Figure 9 in the PCA9509D,112 datasheet.

Does PCA9509D,112 require external pull-up resistors on port A?

No, the PCA9509D,112 does not require external pull-up resistors on port A. It integrates a 1 mA current-source pull-up on both A1 and A2 pins, eliminating the need for discrete resistors and reducing board space and BOM cost. Port B, however, requires standard external pull-up resistors (e.g., 10 kΩ for 3.3 V operation) as specified in Figure 5 of the datasheet.

Can PCA9509D,112 operate at 400 kHz I²C clock speed?

Yes, the PCA9509D,112 supports Standard-mode and Fast-mode I²C-bus operation up to 400 kHz. However, the actual maximum system clock frequency may be lower due to added propagation delays (e.g., −139 ns to −69 ns A→B, 63 ns to 140 ns B→A) and bus capacitance effects. System validation at target clock rate-including rise/fall time and setup/hold timing-is required per Section 10 of the datasheet.

What happens to PCA9509D,112 I/O pins when power is removed?

When either VCC(A) or VCC(B) is unpowered, all I/O pins (A1, A2, B1, B2) enter a high-impedance state, electrically isolating both buses. This behavior enables safe hot-swap, power-gating, and partial-system shutdown without disturbing connected devices. The EN pin remains inactive until both supplies exceed their enable thresholds (VCC(A) > 0.8 V, VCC(B) > 2.5 V).

Is PCA9509D,112 pin-compatible with PCA9509DP or PCA9509GM?

Yes, PCA9509D,112 (SO8), PCA9509DP (TSSOP8), and PCA9509GM (XQFN8) share identical pin functions and electrical specifications per Table 3 and Figure 2–4 of the datasheet. They differ only in package type and thermal/mechanical characteristics. Layout redesign is required for package substitution, but schematic integration and firmware interaction remain unchanged across all variants.