Texas Instruments PCA9543AD

Overview

PCA9543AD from Texas Instruments is a 2-channel bidirectional I²C bus switch with interrupt logic and active-low reset, supporting Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation, voltage-level translation between 1.8-V/2.5-V/3.3-V and 5-V buses, and dual-channel selection via an 8-bit I²C control register - used in server backplanes to isolate conflicting temperature sensor addresses.

For engineers reviewing the PCA9543AD datasheet, PCA9543AD pinout, PCA9543AD application, or PCA9543AD equivalent, key selection considerations include channel-selectable I²C isolation, dual interrupt input handling (INT0/INT1), active-low reset recovery from stuck-bus conditions, and 2.3-V to 5.5-V supply operation with 5.5-V tolerant I/O pins.

Technical Context

The PCA9543AD implements two independent bidirectional pass-gate switches controlled by an 8-bit I²C register (B0/B1 bits), enabling selective routing of SDA/SCL from master to either SC0/SD0, SC1/SD1, or both channels simultaneously. Its interrupt logic performs AND of INT0 and INT1 inputs to drive open-drain INT output.

Each channel supports independent voltage-level translation via external pull-up resistors tied to distinct VDPUx references (VDPU0, VDPU1, VDPUM), allowing interoperability across 1.8-V, 2.5-V, 3.3-V, and 5-V I²C domains without level-shifter ICs. The device includes power-on reset (VPOR = 1.6–2.1 V at 5 V) and active-low hardware reset (tWL = 4 ns min) to recover from bus lockup.

Key Specifications

Pinout & Package

TSSOP-14 package (5.00 mm × 4.40 mm body size), 14-pin surface-mount with exposed pad not specified; RoHS-compliant, lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C bus switch applications.

Compared with TCA9544A and PCA9546AD, the PCA9543AD uniquely delivers dual-channel switching with integrated interrupt logic and hardware reset in a compact TSSOP-14 package - making it optimal for space-constrained, fault-resilient 2-bus systems where interrupt awareness is critical.

Availability

PCA9543AD is available at Aetrix Electronics and suitable for server backplanes, industrial PLCs, telecom routers, and factory automation systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for PCA9543AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.

The PCA9543AD belongs to TI's I²C switch and multiplexer product line, engineered specifically to resolve I²C address conflicts, enable voltage-domain bridging, and provide robust bus isolation in high-density embedded systems.

FAQ

What is the I²C address configuration method for the PCA9543AD?

The PCA9543AD uses two hardware address pins (A0 and A1) to set its 7-bit I²C slave address, yielding four possible addresses: 0x70 (A1=0, A0=0), 0x71 (A1=0, A0=1), 0x72 (A1=1, A0=0), and 0x73 (A1=1, A0=1). These pins must be hard-wired to VCC or GND - floating connections are not permitted. The PCA9543AD does not support software-configurable addressing.

How does the PCA9543AD handle voltage-level translation between different I²C buses?

The PCA9543AD enables voltage-level translation by allowing independent pull-up resistors on each I²C segment: master-side SDA/SCL pull-ups to VDPUM, Channel 0 (SD0/SC0) to VDPU0, and Channel 1 (SD1/SC1) to VDPU1. Since all I/O pins are 5.5-V tolerant and the switch pass gates are VCC-referenced, 1.8-V, 2.5-V, or 3.3-V slaves can interoperate with a 5-V master without external level shifters - provided pull-up voltages match respective bus domains.

What happens to the PCA9543AD channels during power-up or reset?

During power-up, the PCA9543AD performs an internal power-on reset (POR) when VCC rises above VPOR (1.6–2.1 V at 5 V), initializing the control register to 0x00 and deselecting all channels. Similarly, asserting the active-low RESET pin for ≥4 ns forces the same reset state. In both cases, the device enters a known safe condition: no channel is active, INT is high-impedance (open-drain), and all interrupt flags are cleared - preventing unintended bus coupling at startup.

Can the PCA9543AD's interrupt inputs be used for general-purpose signaling?

Yes - the INT0 and INT1 inputs on the PCA9543AD are general-purpose, active-low, 5.5-V tolerant inputs that do not require the associated channel to be selected for detection. When interrupt functionality is unused, they may serve as auxiliary GPIO inputs (e.g., for status flags or fault indicators), provided each is pulled up to its respective VDPUx voltage with a resistor. Their state is reflected in bits 4 and 5 of the control register during reads, regardless of channel enable status.

What is the maximum capacitive load supported on each channel of the PCA9543AD?

The PCA9543AD is characterized for I²C bus capacitance up to 400 pF per channel (CL ≤ 400 pF), consistent with Fast-Mode timing requirements. Its typical input capacitance is 4–6 pF per pin (Ci), and off-state output capacitance (Cio(OFF)) is 6–8 pF. To maintain reliable 400-kHz operation, total bus capacitance - including PCB traces, connectors, and downstream devices - must remain ≤400 pF. Exceeding this limit risks setup/hold time violations and clock stretching, especially with longer traces or multiple slaves per channel.