Texas Instruments PCA9543ADR

Overview

PCA9543ADR from Texas Instruments is a 2-channel bidirectional I²C bus switch with interrupt logic and active-low reset, supporting Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation, voltage-level translation between 1.8-V/2.5-V/3.3-V and 5-V buses, and dual independent interrupt inputs (INT0/INT1) with ANDed open-drain output (INT). It enables I²C slave address conflict resolution in multi-sensor systems.

For engineers reviewing the PCA9543ADR datasheet, PCA9543ADR pinout, PCA9543ADR application, or PCA9543ADR equivalent, key selection criteria include channel-selectable I²C isolation, interrupt aggregation for fault detection, reset recovery from stuck-bus conditions, and voltage-translation capability across mixed-voltage I²C subsystems.

Technical Context

The PCA9543ADR implements two independent bidirectional pass-gate switches controlled via an 8-bit I²C-accessible register, where bits B0 and B1 determine channel enable state (00 = both deselected; 01/10/11 = Channel 0 only / Channel 1 only / both enabled). Its interrupt logic monitors INT0 and INT1 asynchronously and drives the shared INT output low when either input is asserted - without requiring channel activation.

Reset functionality operates independently of I²C communication: asserting RESET low for ≥4 ns resets the internal state machine and forces both channels to deselect, recovering from downstream bus lockup. The device supports hot insertion and exhibits no power-up glitch due to built-in power-on reset (POR) that triggers at VCC ≥ 1.6 V (typical) and releases at ≥2.1 V.

Key Specifications

Pinout & Package

TSSOP-14 package (5.00 mm × 4.40 mm), thermally optimized for industrial PCB layouts with exposed pad not present; RoHS-compliant, lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C bus switching applications.

Compared with TCA9544APWR and PCA9546APW, the PCA9543ADR delivers optimal balance of channel count, interrupt capability, and compact TSSOP-14 packaging - making it the sole fit for cost-sensitive, space-constrained, and fault-detection-critical 2-channel I²C isolation.

Availability

PCA9543ADR is available at Aetrix Electronics and suitable for server baseboard management, industrial sensor hubs, and telecom router monitoring requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for PCA9543ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in I²C interface solutions and industrial-grade reliability.

The PCA9543ADR belongs to TI's I²C switch and multiplexer product line, designed specifically to resolve slave address conflicts, enable mixed-voltage I²C communication, and provide robust fault detection in high-density embedded systems.

FAQ

What is the I²C slave address range supported by the PCA9543ADR?

The PCA9543ADR supports four fixed I²C slave addresses: 0x70, 0x71, 0x72, and 0x73. These are determined by the logic states of the A0 and A1 pins - A1:A0 = 00, 01, 10, or 11 respectively. All addresses are 7-bit, with the R/W bit appended during transmission. The PCA9543ADR does not support address auto-detection or dynamic reconfiguration.

Does the PCA9543ADR require external pull-up resistors on all I²C lines?

Yes, the PCA9543ADR requires external pull-up resistors on SDA, SCL, INT, INT0, INT1, and RESET lines. Each downstream channel (SD0/SC0 and SD1/SC1) must use its own pull-up network referenced to its respective VDPU rail (VDPU0 or VDPU1), while the upstream SDA/SCL lines connect to VDPUM. No internal pull-ups are integrated.

Can the PCA9543ADR translate between 1.8-V and 5-V I²C buses simultaneously?

Yes, the PCA9543ADR supports simultaneous 1.8-V and 5-V translation: configure VDPU0 = 1.8 V for Channel 0 (SD0/SC0) and VDPU1 = 5 V for Channel 1 (SD1/SC1), with VDPUM = 3.3 V for the upstream SDA/SCL. This allows a 1.8-V sensor and 5-V EEPROM to coexist on the same master-controlled I²C bus without additional level-shifting components.

How does the PCA9543ADR handle interrupt signals when no channel is selected?

The PCA9543ADR monitors INT0 and INT1 continuously, regardless of channel selection state. If either INT0 or INT1 is pulled low, the INT output will assert low and the corresponding bit (bit 4 for INT0, bit 5 for INT1) will be set in the control register - even when both channels are deselected. This enables preemptive fault detection before channel activation.

What happens to the PCA9543ADR's switch state during a power-on reset?

During power-on reset, the PCA9543ADR initializes its control register to 0x00, deselecting both channels and clearing all interrupt flags. This occurs automatically when VCC rises above the POR threshold (~2.1 V). The device remains in this safe, high-impedance state until the master writes a new configuration - ensuring no unintended bus contention at startup.