NXP Semiconductors PCA9547D,112

Overview

PCA9547D,112 from NXP Semiconductors is an octal bidirectional I²C-bus multiplexer with active-low reset, enabling one upstream I²C master to selectively route communication to eight downstream I²C buses. It features voltage-level translation between 1.8 V, 2.5 V, 3.3 V, and 5 V domains, operates from 2.3 V to 5.5 V supply, supports up to 400 kHz Fast-mode I²C, and powers up with Channel 0 enabled for immediate bus access in embedded sensor or peripheral expansion systems.

For engineers reviewing the PCA9547D,112 datasheet, PCA9547D,112 pinout, PCA9547D,112 application, or PCA9547D,112 equivalent, key selection criteria include its 24-pin SO24 package, 1-of-8 channel selection via I²C control register, 5 V-tolerant I/O, low Ron (≤30 Ω), and integrated reset recovery for stuck-bus fault handling in multi-slave industrial control designs.

Technical Context

The PCA9547D,112 implements a hardware-controlled pass-gate multiplexer architecture with independent SCL/SDA channel switching. Its control register uses four LSBs (B3–B0) to select exactly one of eight SCx/SDx pairs, with all channels deselected except Channel 0 at power-on or reset.

Reset functionality is implemented as an asynchronous active-low input that forces the internal state machine into default mode-deselecting all channels except Channel 0-enabling bus recovery without host intervention. Voltage translation is achieved by leveraging VDD as the clamp reference for pass-gate output voltage (Vo(mux)), allowing interoperability across mixed-voltage I²C subsystems without external level shifters.

Key Specifications

Pinout & Package

PCA9547D,112 is housed in a plastic small outline package (SO24, SOT137-1) with 24 leads and 7.5 mm body width. The package includes exposed thermal pad grounding via VSS pin and requires standard reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C bus multiplexer applications.

Compared with TCA9548A and PCA9544A, the PCA9547D,112 uniquely combines 8-channel switching, hardware RESET, and VDD-based voltage translation in a single SO24 package-making it the only option for robust, mixed-voltage I²C expansion where bus fault recovery and domain interoperability are non-negotiable.

Availability

PCA9547D,112 is available at Aetrix Electronics and suitable for industrial sensor hubs, automotive body control units, and automated test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for PCA9547D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with broad analog, digital, and mixed-signal product portfolios.

The PCA9547D,112 belongs to NXP's I²C-bus multiplexer family, designed specifically to solve bus contention, address collision, and mixed-voltage interoperability challenges in resource-constrained embedded systems.

FAQ

What is the function of the RESET pin on the PCA9547D,112?

The RESET pin on the PCA9547D,112 is an active-low asynchronous input that forces the device into its default state-deselecting all downstream channels except Channel 0-within 500 ns. This recovers the upstream I²C bus when a downstream slave holds SDA or SCL low, and requires an external pull-up resistor to VDD per datasheet Section 6.3.

Does the PCA9547D,112 support voltage level translation between 1.8 V and 5 V I²C buses?

Yes, the PCA9547D,112 supports bidirectional voltage translation between 1.8 V, 2.5 V, 3.3 V, and 5 V I²C domains by using VDD as the clamp reference for Vo(mux). When VDD is set to 3.3 V, it limits downstream output voltage to ≤2.8 V (per Table 7), enabling safe communication between a 5 V master and 1.8 V slaves using appropriate pull-up resistors on each channel.

How many PCA9547D,112 devices can share the same I²C bus?

Up to eight PCA9547D,112 devices can coexist on a single I²C bus using the three hardware address pins (A0, A1, A2), which configure the 3-bit portion of the 7-bit slave address (1110 A2 A1 A0 R/W). Each device must have a unique A0–A2 combination; no internal pull-ups exist on these pins, so external termination is required.

What is the maximum clock frequency supported by the PCA9547D,112?

The PCA9547D,112 supports I²C clock frequencies up to 400 kHz, compliant with Fast-mode I²C specifications. Its propagation delay is ≤0.3 ns (per Table 9), and timing parameters-including tLOW, tHIGH, and tSU;DAT-are validated for operation across the full 2.3 V to 5.5 V supply range, ensuring reliable signaling at maximum speed.

Is the PCA9547D,112 pin-compatible with other members of the PCA954x family?

The PCA9547D,112 shares identical pinout and control register structure with PCA9544A (4-channel) and PCA9548A (8-channel, no RESET) in SO24 packaging. However, PCA9547D,112 is not pin-compatible with PCA9548A due to the dedicated RESET pin (Pin 3), which maps to NC on PCA9548A-requiring PCB layout revision for substitution.