NXP Semiconductors PCA9547D,118

Overview

PCA9547D,118 from NXP Semiconductors is an octal bidirectional I²C-bus multiplexer with active-low reset, enabling one upstream master to selectively route communication to eight downstream I²C buses. It features voltage-level translation (1.8 V to 5 V), low ON-resistance (≤30 Ω), and operates from 2.3 V to 5.5 V supply. Used in server management, industrial PLCs, and multi-sensor systems where bus isolation and mixed-voltage interoperability are required.

For engineers reviewing the PCA9547D,118 datasheet, PCA9547D,118 pinout, PCA9547D,118 application, or PCA9547D,118 equivalent, key selection criteria include channel-select timing, reset recovery behavior, VDD-dependent Vo(mux) clamping, thermal resistance (77 °C/W for SO24), and compatibility with SMBus standards up to 400 kHz.

Technical Context

The PCA9547D,118 implements a hardware-controlled 1-of-8 channel selection via its 4-bit control register, where only one SCx/SDx pair is enabled per transaction after STOP condition assertion. Its pass-gate architecture uses VDD as a voltage clamp reference, allowing bidirectional level shifting without external translators.

Internal state machine resets on power-up to Channel 0 by default and recovers from stuck-bus faults via active-low RESET input (tw(rst)L ≥ 4 ns). All I/O pins are 5 V tolerant, and the device supports hot insertion with no glitch on power-up and standby current as low as 0.1 µA at 3.6 V.

Key Specifications

Pinout & Package

PCA9547D,118 is supplied in SO24 (SOT137-1) package: plastic small outline, 24-lead, 7.5 mm body width, with standard marking and reel packaging (13″ Q1/T1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C multiplexer applications.

Compared with TCA9548A and PCA9546ADW, PCA9547D,118 uniquely combines hardware RESET recovery, full 8-channel capacity, and SO24 mechanical compatibility - making it optimal for mission-critical industrial and telecom infrastructure where deterministic bus fault handling is mandatory.

Availability

PCA9547D,118 is available at Aetrix Electronics and suitable for server baseboard management, industrial PLC I/O expansion, and multi-sensor IoT gateway designs requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for PCA9547D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.

The PCA9547 product line delivers scalable I²C bus expansion with integrated voltage translation and fault recovery - designed specifically for systems needing reliable, low-power, multi-peripheral communication in space-constrained and mixed-voltage environments.

FAQ

What is the function of the RESET pin on the PCA9547D,118?

The RESET pin on the PCA9547D,118 is an active-low asynchronous input that forces deselection of all downstream channels except Channel 0 and resets the internal I²C state machine. This recovers communication when any downstream bus is stuck LOW, and requires a minimum pulse width of 4 ns. The pin must be pulled up to VDD externally.

Does the PCA9547D,118 support voltage translation between 1.8 V and 5 V I²C buses?

Yes, the PCA9547D,118 supports bidirectional voltage translation between 1.8 V, 2.5 V, 3.3 V, and 5 V buses. Its pass-gate architecture uses VDD as the clamping reference: setting VDD to 3.3 V allows safe interfacing of a 5 V upstream master with 1.8 V downstream slaves, provided appropriate pull-up resistors are used per channel.

How many PCA9547D,118 devices can share the same I²C bus?

Up to eight PCA9547D,118 devices can share the same upstream I²C bus. This is enabled by three hardware address pins (A0, A1, A2), each configurable HIGH or LOW, yielding eight unique 7-bit slave addresses (1110A2A1A0R/W). No internal pull-ups exist on these pins - external biasing is required.

What is the maximum I²C clock frequency supported by the PCA9547D,118?

The PCA9547D,118 supports I²C clock frequencies up to 400 kHz (Fast-mode), compliant with SMBus standards. Propagation delay from SDA to SDx or SCL to SCx is ≤0.3 ns, ensuring timing integrity across all eight channels under standard and fast-mode conditions.

Is the PCA9547D,118 pin-compatible with other members of the PCA954X family?

The PCA9547D,118 is not pin-compatible with PCA9546 (SO16) or PCA9548A (TSSOP24/HVQFN24), though it shares functional equivalence and register mapping with PCA9548A. Its SO24 footprint (SOT137-1) is unique within the family and requires dedicated PCB layout - no mechanical interchangeability exists with other variants.