NXP Semiconductors PCA9555N,112

Overview

The PCA9555N,112 from NXP Semiconductors is a 16-bit I²C-bus/SMBus GPIO expander in a 24-pin DIP package, providing two configurable 8-bit I/O ports with individual direction control, polarity inversion, and active-low open-drain interrupt output. It operates from 2.3 V to 5.5 V, tolerates 5 V on I/O pins, supports up to 400 kHz I²C clocking, and targets embedded system expansion for push buttons, LEDs, sensors, and fan control.

For engineers reviewing the PCA9555N,112 datasheet, PCA9555N,112 pinout, PCA9555N,112 application, or PCA9555N,112 equivalent, this page delivers verified electrical specs, DIP24 pin mapping, real-world use cases in industrial HMI and sensor subsystems, and validated alternative parts with documented functional differences.

Technical Context

The PCA9555N,112 implements dual 8-bit configuration registers (Port 0 and Port 1) that define each I/O as input or output independently; input port registers reflect actual pin states regardless of direction setting, while output port registers drive logic levels only when configured as outputs. Polarity inversion registers allow software-defined active-HIGH/LOW interpretation of input data without external hardware changes.

Its interrupt output activates on state change of any input-configured I/O pin and clears only upon reading the corresponding input port register - not by reading the opposite port - enabling precise edge detection in multi-port systems. Three address pins (A0–A2) support up to eight devices on one I²C bus with fixed base address 0x20, matching PCA9554 compatibility.

Key Specifications

Pinout & Package

PCA9555N,112 uses the plastic dual in-line package (DIP24), SOT101-1, with 24 leads (600 mil width). Pin 1 is INT (interrupt output); pins 4–11 and 13–20 are bidirectional I/Os grouped as Port 0 (IO0_0 to IO0_7) and Port 1 (IO1_0 to IO1_7); address pins A0–A2 occupy pins 21, 2, and 3; SCL/SDA are pins 22/23; VDD/VSS are pins 24/12.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C GPIO expander applications.

Compared with PCA9555N,112, TCA6424A offers higher I/O density and integrated pull-ups but removes polarity inversion flexibility, while PCA9554A reduces cost and complexity at the expense of interrupt functionality and scalability - making PCA9555N,112 optimal for balanced performance in event-driven industrial systems.

Availability

PCA9555N,112 is available at Aetrix Electronics and suitable for industrial HMI, sensor subsystem monitoring, fan control, and LED indicator bank management requiring stable component supply across extended product lifecycles.

Supply support for PCA9555N,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in interface and power management ICs.

The PCA9555N,112 belongs to NXP's I²C-bus I/O expander family, designed specifically to simplify GPIO expansion in resource-constrained embedded systems while maintaining industrial-grade reliability and interoperability.

FAQ

What is the I²C address range supported by the PCA9555N,112?

The PCA9555N,112 uses three hardware address pins (A0, A1, A2) to configure its 7-bit I²C slave address. With base address 0x20, it supports addresses 0x20 through 0x27 - enabling up to eight PCA9555N,112 devices on a single I²C bus without address conflict. This matches the PCA9554 address map for seamless migration.

Does the PCA9555N,112 require external pull-up resistors on SCL and SDA lines?

Yes, the PCA9555N,112 requires external pull-up resistors on both SCL and SDA lines, as specified in the I²C-bus standard. The device includes internal noise filters on these inputs but does not integrate pull-up resistors. Typical values are 2.2 kΩ to 4.7 kΩ for 100 kHz operation and 1 kΩ for 400 kHz fast-mode, referenced to VDD.

How does the interrupt output of the PCA9555N,112 behave after a state change?

The PCA9555N,112 interrupt output (INT) goes LOW when any input-configured I/O pin changes state relative to its input port register value. The interrupt remains asserted until the corresponding input port register (Port 0 or Port 1) is read - reading the opposite port does not clear it. This ensures precise source identification in multi-port systems.

Can the PCA9555N,112 drive LEDs directly?

Yes, the PCA9555N,112 can drive LEDs directly when configured as open-drain outputs with external current-limiting resistors. Each I/O pin sinks up to 8 mA at VOL = 0.5 V (VDD = 2.3–5.5 V), supporting standard 2–20 mA LEDs. For higher brightness, use external FETs - the PCA9555N,112 is not intended for high-current loads.

What happens to the I/O pins during power-on reset of the PCA9555N,112?

During power-on reset, all 16 I/O pins of the PCA9555N,112 default to high-impedance inputs with internal weak pull-ups to VDD. Configuration registers initialize to 0xFF (all inputs), output registers to 0xFF (all HIGH), and polarity inversion registers to 0x00 (no inversion). This safe default prevents bus contention and ensures predictable startup behavior.