NXP Semiconductors PCA9559PW,112

Overview

PCA9559PW,112 from NXP Semiconductors is a 20-pin TSSOP I²C-bus EEPROM DIP switch IC with 6-bit non-volatile register storage, 5-bit multiplexed open-drain outputs, and one latched open-drain output. It operates from 3.0 V to 3.6 V, supports up to 400 kHz I²C clock frequency, and retains configuration data for up to 10 years. It is used between CPU and VRM for VID voltage configuration in desktop/server systems.

For engineers reviewing the PCA9559PW,112 datasheet, PCA9559PW,112 pinout, PCA9559PW,112 application, or PCA9559PW,112 equivalent, this page delivers verified functional architecture, I²C address mapping (0x48–0x4B), override/latch behavior, EEPROM endurance (100k write cycles), and thermal resistance (146 °C/W) - all critical for jumperless motherboard design and VID tuning.

Technical Context

The PCA9559PW,112 implements a dual-source 5-bit 2-to-1 multiplexer: MUX_SELECT selects between external MUX_IN pins (A–E) or internal EEPROM register bits for MUX_OUT outputs (A–E). The NON_MUXED_OUT output is latched on MUX_SELECT rising edge and reflects the EEPROM bit independent of multiplexer state.

Its I²C interface uses two hardware address pins (A0, A1) enabling four unique addresses (0x48–0x4B); Write Protect (WP) disables EEPROM writes when high; OVERRIDE_N forces all outputs low asynchronously. Internal pull-ups exist on OVERRIDE_N, WP, and MUX_SELECT, and all I/Os are 5 V/2.5 V tolerant.

Key Specifications

Pinout & Package

TSSOP20 package (SOT360-1), 4.4 mm body width, 0.65 mm lead pitch, 1.1 mm max height - optimized for high-density motherboard routing and reflow soldering per J-STD-020D.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-configurable VID switch applications.

Compared with PCA9559PW,112, PCA9557PW,118 offers more I/O but no VID-specific features like latched output or hardware override; MAX6957ATL+ provides higher channel count and LED drive capability but lacks multiplexer architecture and VRM-compatible signal timing - making PCA9559PW,112 uniquely suited for CPU voltage ID configuration.

Availability

PCA9559PW,112 is available at Aetrix Electronics and suitable for desktop motherboard design, server platform voltage tuning, and telecom equipment configuration requiring stable component supply and long-term EEPROM retention.

Supply support for PCA9559PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The PCA9559PW,112 belongs to NXP's I²C peripheral portfolio designed specifically for jumperless system configuration - targeting CPU VID management, VRM interface, and hardware abstraction in high-reliability computing platforms.

FAQ

What is the I²C address range supported by PCA9559PW,112?

The PCA9559PW,112 supports four I²C addresses: 0x48, 0x49, 0x4A, and 0x4B. These are determined by the logic states of A0 and A1 pins, which have internal pull-up resistors (100–150 kΩ). When both pins are left floating, PCA9559PW,112 defaults to address 0x48. This addressing scheme allows up to four PCA9559PW,112 devices on the same I²C bus without conflict.

How does the OVERRIDE_N pin function in PCA9559PW,112?

The OVERRIDE_N pin on PCA9559PW,112 is an active-low signal that forces all five MUX_OUT outputs and the NON_MUXED_OUT output to logic 0, regardless of EEPROM contents, MUX_SELECT state, or MUX_IN values. It operates asynchronously and has an internal pull-up resistor. This feature provides hardware-level fail-safe reset capability for CPU VID lines, ensuring safe low-voltage operation during fault conditions or system initialization.

Can PCA9559PW,112 operate outside its specified 3.0 V to 3.6 V supply range?

No, PCA9559PW,112 is characterized and guaranteed to operate only within 3.0 V to 3.6 V. Operation below 3.0 V may cause improper EEPROM write verification or I²C state machine lockup; operation above 3.6 V exceeds absolute maximum ratings and risks permanent damage. The Power-On Reset (POR) threshold is 1.9–2.6 V, but functional operation requires VCC ≥ 3.0 V per the recommended operating conditions table in the datasheet.

What is the role of the MUX_SELECT pin in PCA9559PW,112 operation?

The MUX_SELECT pin controls data source selection and latching behavior in PCA9559PW,112. When low, it routes EEPROM register bits to MUX_OUT outputs and makes NON_MUXED_OUT transparent to the EEPROM bit. When high, it routes MUX_IN inputs to MUX_OUT outputs and latches the current EEPROM value onto NON_MUXED_OUT. This dual-function pin enables seamless transition between hardware-defined and software-defined VID configurations.

How many write cycles can the EEPROM in PCA9559PW,112 endure?

The EEPROM in PCA9559PW,112 is rated for a minimum of 100,000 write cycles and guarantees data retention for at least 10 years under normal operating conditions. Each write cycle includes internal verify and auto-erase operations. Write access is disabled when the WP pin is high, protecting stored VID values from accidental modification during system runtime or firmware updates.