NXP Semiconductors PCA9559PW/G,118

Overview

PCA9559PW/G,118 from NXP Semiconductors (formerly Philips) is a 20-pin TSSOP I²C EEPROM DIP switch IC used for jumperless system configuration in CPU VID voltage control circuits. It integrates a 6-bit non-volatile register (5 multiplexed + 1 latched), 5-bit 2-to-1 multiplexer, override input, write-protect pin, and supports 4-device I²C addressing via A0/A1. It operates from 3.0 V to 3.6 V and enables dynamic CPU voltage adjustment in desktop/server VRM interfaces.

For engineers reviewing the PCA9559PW/G,118 datasheet, PCA9559PW/G,118 pinout, PCA9559PW/G,118 application, or PCA9559PW/G,118 equivalent, this page delivers verified functional architecture, I²C address mapping, VID configuration timing behavior, EEPROM endurance (100k cycles), and real-world use cases in mobile/desktop performance/sleep mode switching.

Technical Context

The PCA9559PW/G,118 implements a dual-source 5-bit multiplexer where MUX_SELECT selects between external hardware inputs (MUX_IN A–E) or internal EEPROM register values for MUX_OUT A–E outputs. The NON_MUXED_OUT pin is latched on MUX_SELECT rising edge and retains its value until next latch event.

Its I²C interface uses a 7-bit address with two programmable bits (A1/A0), enabling up to four devices on one bus. Write protection is controlled by the WP pin: logic 0 enables EEPROM writes; logic 1 disables them. Factory default EEPROM contents are all zeros.

Key Specifications

Pinout & Package

PCA9559PW/G,118 is housed in a 20-pin plastic thin shrink small outline package (TSSOP), SOT360-1, body width 4.4 mm, lead pitch 0.65 mm, suitable for high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-configurable VID switch applications.

Compared with PCA9559PW/G,118, PCA9555PW,118 offers higher I/O count but no non-volatile storage or VID-specific control logic, while MAX6958ATL+ serves entirely different display-driving functions-neither provides the integrated EEPROM-mux-latch architecture required for reliable, software-controlled CPU voltage configuration.

Availability

PCA9559PW/G,118 is available at Aetrix Electronics and suitable for desktop motherboard design, server VRM integration, telecom baseband power sequencing, and mobile platform deep-sleep voltage control requiring stable component supply and long-term obsolescence support.

Supply support for PCA9559PW/G,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors, formerly Philips Semiconductors, is a global leader in high-performance mixed-signal ICs, with expertise in interface, power management, and automotive electronics.

The PCA9559PW/G,118 belongs to NXP's legacy I²C peripheral portfolio designed specifically for eliminating mechanical configuration elements in computing and communications infrastructure.

FAQ

What is the primary function of the PCA9559PW/G,118 in CPU voltage control systems?

The PCA9559PW/G,118 serves as an I²C-programmable, non-volatile VID switch that replaces physical DIP switches on motherboards. It stores two sets of voltage identification codes-one in EEPROM and one from hardware pins-and selects between them using MUX_SELECT to configure the VRM. This enables dynamic CPU voltage adjustment for performance or power-saving modes without manual intervention. The PCA9559PW/G,118 is essential for achieving software-controlled VID transitions in modern desktop and server platforms.

How does the OVERRIDE_N pin affect the outputs of the PCA9559PW/G,118?

The OVERRIDE_N pin is an active-low signal that forces all five MUX_OUT outputs and the NON_MUXED_OUT output to logic 0 regardless of EEPROM contents, MUX_IN states, or MUX_SELECT level-provided MUX_SELECT is also logic 0. This provides a hardware-level safety mechanism to immediately disable VID signals during fault conditions or thermal emergencies. The PCA9559PW/G,118 maintains this override state until OVERRIDE_N is deasserted and MUX_SELECT is toggled to restore normal operation.

Can the PCA9559PW/G,118 be used with 5 V I²C hosts despite its 3.3 V supply?

Yes-the PCA9559PW/G,118 features 5 V tolerant I²C SCL and SDA inputs, as well as 5 V tolerant MUX_IN, OVERRIDE_N, WP, and MUX_SELECT pins. Its internal level-shifting circuitry allows direct connection to 5 V microcontrollers or baseband processors without external translators. However, VCC must remain within 3.0 V to 3.6 V, and all outputs (MUX_OUT/NON_MUXED_OUT) are open-drain and require pull-up resistors referenced to the target VID rail (typically 3.3 V or 5 V). The PCA9559PW/G,118 thus bridges mixed-voltage system domains safely.

What is the significance of the 100,000 write-cycle EEPROM specification for the PCA9559PW/G,118?

The 100,000 minimum write cycles guarantee long-term reliability for infrequent but mission-critical VID reprogramming events-such as BIOS updates, factory calibration, or field firmware patches. Unlike volatile registers, this endurance rating ensures the PCA9559PW/G,118 retains correct voltage settings across decades of operation, even under worst-case thermal stress. Each write cycle includes built-in write-protection (via WP pin) and automatic write-time delay (~15 ms), preventing corruption during brown-out or bus contention. The PCA9559PW/G,118 is therefore qualified for deployment in enterprise servers and telecom infrastructure where field replaceability is costly.

How does the MUX_SELECT pin control both multiplexer routing and latching behavior in the PCA9559PW/G,118?

MUX_SELECT acts as a dual-function control: when low, it routes EEPROM register values to MUX_OUT A–E and makes NON_MUXED_OUT transparent to the EEPROM bit; when high, it routes MUX_IN A–E to MUX_OUT A–E and latches the current EEPROM value onto NON_MUXED_OUT. The latch occurs precisely on the rising edge of MUX_SELECT, freezing the selected VID bit for stable VRM interface timing. This synchronous behavior ensures deterministic voltage transitions during OS power-state changes. The PCA9559PW/G,118 thus delivers coordinated, glitch-free VID updates without requiring additional clock or strobe signals.