NXP Semiconductors PCA9560PW,118

Overview

PCA9560PW,118 from NXP Semiconductors is a dual 5-bit multiplexed 1-bit latched I²C-bus EEPROM DIP switch in TSSOP20 package, used for CPU VID configuration between processor and VRM. It provides two independent 6-bit non-volatile registers, 5-bit external hardware inputs, and open-drain multiplexed outputs to support performance/deep-sleep/deeper-sleep voltage modes in desktop and server platforms.

For engineers reviewing the PCA9560PW,118 datasheet, PCA9560PW,118 pinout, PCA9560PW,118 application, or PCA9560PW,118 equivalent, key selection factors include I²C/SMBus programmability, dual-register VID selection, write-protect control, 3.0–3.6 V operation, and drop-in compatibility with PCA9559 in CPU voltage configuration circuits.

Technical Context

The PCA9560PW,118 implements a 5-bit 3-to-1 multiplexer with latch control, selecting output sources among two internal 6-bit EEPROM registers or five external hardware pins via MUX_SELECT_0/1. Its I²C interface supports standard- and fast-mode (up to 400 kHz) with internal pull-ups on control inputs and active-high write protection.

It resides in the CPU voltage identification path, overriding default VID codes sent by the processor to the VRM. The NON-MUXED_OUT pin delivers the 6th MSB of the selected register as a latched output, while five open-drain MUX_OUT pins deliver the lower 5 bits - enabling full 6-bit VID code generation without physical DIP switches.

Key Specifications

Pinout & Package

TSSOP20 package (SOT360-1), 4.4 mm body width, 0.65 mm lead pitch, surface-mount compatible with reflow soldering per AN10365.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-configurable VID switch applications.

Compared with PCA9559PW,118 and PCA9555PW,118, the PCA9560PW,118 uniquely delivers triple-state VID selection with hardware/firmware source flexibility and zero-software-change migration path - making it optimal for next-generation CPU voltage configuration where adaptive power states are required.

Availability

PCA9560PW,118 is available at Aetrix Electronics and suitable for desktop motherboard design, server platform tuning, telecom baseband configuration, and industrial embedded controller boot-mode setup requiring stable component supply and long-term lifecycle support.

Supply support for PCA9560PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The PCA9560PW,118 belongs to NXP's I²C peripheral portfolio designed specifically for system-level configuration and power management - targeting CPU voltage ID translation in high-reliability computing platforms.

FAQ

What is the primary function of the PCA9560PW,118 in CPU voltage configuration?

The PCA9560PW,118 serves as an I²C-programmable VID translator between the CPU and VRM, delivering 6-bit voltage identification codes from either two internal EEPROM registers or five external hardware pins. It enables dynamic selection of performance, deep sleep, and deeper sleep voltage states without physical DIP switches - and the PCA9560PW,118 retains its last programmed setting across power cycles.

Does the PCA9560PW,118 support drop-in replacement for the PCA9559PW,118?

Yes, the PCA9560PW,118 is footprint-compatible and functionally backward-compatible with the PCA9559PW,118. When EEPROM register 1 is left at its factory-default all-zero state, MUX_SELECT_1 operates identically to the PCA9559's OVERRIDE# pin. No PCB layout or firmware changes are required to upgrade - and the PCA9560PW,118 adds triple-state VID capability without disrupting existing designs.

How does the write-protect (WP) pin affect EEPROM programming on the PCA9560PW,118?

The WP pin on the PCA9560PW,118 is active-HIGH: when driven HIGH, it blocks all I²C writes to both EEPROM registers, though address and command bytes remain acknowledged. When LOW, writes proceed normally - and the PCA9560PW,118 requires 3.6 ms after a write to accept new I²C commands. Internal pull-up ensures default write protection at power-on, enhancing system safety.

Can the PCA9560PW,118 read external hardware pin states over I²C?

Yes, the PCA9560PW,118 supports reading the current logic states of MUX_IN_A through MUX_IN_E via I²C using the reserved command byte 0xFF. This returns a 5-bit value (padded with two leading zeros) representing the live hardware inputs - a capability absent in the PCA9559PW,118. This feature enables runtime validation of jumperless configuration integrity and the PCA9560PW,118 makes it accessible without additional monitoring circuitry.

What are the voltage tolerance specifications for I/O pins on the PCA9560PW,118?

All digital I/O pins on the PCA9560PW,118 - including SCL, SDA, A0/A1, MUX_SELECT_0/1, MUX_IN_A–E, and outputs - are rated for 5 V and 2.5 V tolerance. This allows direct connection to mixed-voltage logic families without level shifters. Input voltage limits are -1.5 V to +5.5 V (or VDD + 4.0 V, whichever is lower), and the PCA9560PW,118 maintains functional integrity across this range under recommended operating conditions.