NXP Semiconductors PCA9561D,118

Overview

PCA9561D,118 from NXP Semiconductors is a 20-pin I²C-bus EEPROM-based DIP switch replacement IC used for CPU VID configuration between processor and VRM. It integrates four 6-bit non-volatile EEPROM registers, six hardware input pins (MUX_IN_A–F), and six open-drain multiplexed outputs (MUX_OUT_A–F), operating from 3.0 V to 3.6 V supply with 400 kHz I²C-bus support. It enables dynamic voltage tuning in laptop SpeedStep and server power management systems.

For engineers reviewing the PCA9561D,118 datasheet, PCA9561D,118 pinout, PCA9561D,118 application, or PCA9561D,118 equivalent, key selection criteria include non-volatile register count (4×6-bit), I²C address flexibility (A0/A1 → 4-device bus), write-protect control (WP pin), MUX_SELECT source selection behavior, and 5 V/2.5 V tolerant I/O compatibility with legacy VID interfaces.

Technical Context

The PCA9561D,118 implements a dual-source 6-bit multiplexer: MUX_SELECT pin selects between external hardware inputs (MUX_IN_A–F) or internal EEPROM register contents (four 6-bit non-volatile bytes) as output source for MUX_OUT_A–F. I²C-bus commands override MUX_SELECT state, enabling software-controlled VID reconfiguration without hardware changes.

Its I²C interface supports standard- and fast-mode (up to 400 kHz), with slave address determined by A0/A1 pins and R/W bit. Internal Power-On Reset ensures EEPROM byte 0 defaults to all-zeros on power-up when MUX_SELECT = 0, while WP pin disables EEPROM writes when logic high - critical for production voltage lock-down.

Key Specifications

Pinout & Package

TSSOP20 package (SOT360-1), 4.4 mm body width, 0.65 mm lead pitch - optimized for high-density motherboard layouts near CPU socket and VRM.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar VID configuration applications.

Compared with PCA9559PW,118 and PCA9560PW,118, the PCA9561D,118 delivers superior voltage tuning granularity (5 profiles vs. 1 or 2), hardware/software dual-source redundancy, and field-upgradeable VID persistence - making it the only option for adaptive power management in modern mobile and server platforms.

Availability

PCA9561D,118 is available at Aetrix Electronics and suitable for laptop SpeedStep implementation, server CPU voltage tuning, telecom baseband power management, and industrial embedded CPU control requiring stable component supply across multi-year production cycles.

Supply support for PCA9561D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with deep expertise in I²C-bus interface and power management ICs.

The PCA9561D,118 belongs to NXP's I²C-bus configurable logic family, designed specifically to replace mechanical DIP switches in CPU voltage identification circuits - targeting high-reliability, remotely configurable power systems.

FAQ

What is the primary function of the PCA9561D,118 in CPU voltage configuration?

The PCA9561D,118 serves as an I²C-programmable VID translator between CPU and VRM, selecting from four non-volatile EEPROM registers or six hardware inputs to drive six open-drain MUX_OUT lines. It replaces physical DIP switches, enabling dynamic voltage tuning - for example, boosting CPU voltage up to 7.5% for performance gains or lowering it for battery conservation. Its design ensures the PCA9561D,118 retains the last-selected setting across power cycles.

How does the MUX_SELECT pin interact with I²C-bus control in the PCA9561D,118?

The MUX_SELECT pin determines default source selection: logic 0 routes EEPROM byte 0 to MUX_OUT, logic 1 routes MUX_IN inputs. However, I²C-bus commands can override this state - for instance, writing command 0x00 forces EEPROM byte 0 output regardless of MUX_SELECT. This dual-control architecture makes the PCA9561D,118 uniquely suited for systems requiring both hardware fallback and software-defined voltage profiles.

What are the voltage tolerance specifications for PCA9561D,118 I/O pins?

The PCA9561D,118 features 5 V and 2.5 V tolerant inputs and outputs on all MUX_IN, MUX_OUT, SCL, and SDA pins - verified per datasheet Table 13. This allows direct interfacing with legacy VRM VID buses operating at either voltage level without external level shifters. The PCA9561D,118 maintains full functionality across its 3.0 V–3.6 V supply range while tolerating these higher I/O voltages safely.

Can the PCA9561D,118 be used in systems requiring multiple simultaneous VID configurations?

Yes - the PCA9561D,118 supports five distinct VID configurations: four stored in independent 6-bit non-volatile EEPROM registers (accessible via I²C) plus one defined by external MUX_IN pins. This enables use cases like multi-profile laptop power plans (performance, balanced, battery saver) or server thermal/power states. Each EEPROM register persists independently, and the PCA9561D,118 allows runtime switching between them without power interruption.

What protection mechanisms prevent unintended writes to PCA9561D,118 EEPROM registers?

The PCA9561D,118 incorporates dual write protection: hardware-level via the WP pin (logic high disables all EEPROM writes) and time-based via internal write cycle timing - after any EEPROM write, the device ignores I²C addresses for 3.6 ms to complete programming. Additionally, factory defaults are all zeros, and the PCA9561D,118 requires explicit command-byte addressing (0x00–0x03) to access individual registers - preventing accidental overwrites during bus traffic.