NXP Semiconductors PCA9561PW,112

Overview

PCA9561PW,112 from NXP Semiconductors is a 20-pin I²C-bus EEPROM-based DIP switch replacement IC used for CPU VID configuration between processor and VRM. It integrates four 6-bit non-volatile EEPROM registers, six hardware input pins (MUX_IN_A–F), and six open-drain multiplexed outputs (MUX_OUT_A–F), operating at 3.0–3.6 V with 400 kHz I²C-bus support. It enables dynamic voltage tuning in laptop SpeedStep and server power management systems.

For engineers reviewing the PCA9561PW,112 datasheet, PCA9561PW,112 pinout, PCA9561PW,112 application, or PCA9561PW,112 equivalent, key selection criteria include EEPROM register count (4×6-bit), MUX_SELECT-controlled source selection (EEPROM vs. hardware inputs), write-protect (WP) functionality, I²C address flexibility (A0/A1), and 5 V/2.5 V tolerant I/O compatibility.

Technical Context

The PCA9561PW,112 implements a dual-source 6-bit multiplexer architecture: MUX_SELECT pin selects between internal EEPROM register contents (four selectable 6-bit values) or external MUX_IN_A–F hardware inputs. I²C-bus control can override MUX_SELECT to force EEPROM sourcing regardless of pin state.

Its I²C interface supports standard- and fast-mode (up to 400 kHz), with slave address determined by A0/A1 pins (four possible addresses). Non-volatile EEPROM retains settings across power cycles, and WP pin enables hardware-level write protection-logic 0 allows writes, logic 1 blocks them.

Key Specifications

Pinout & Package

TSSOP20 package (SOT360-1), 20-lead plastic thin shrink small outline, body width 4.4 mm, lead pitch 0.65 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar VID configuration applications.

Compared with PCA9559PW,118 and PCA9560PW,112, the PCA9561PW,112 delivers greater configuration depth (four EEPROM registers), runtime source control via I²C override, and full MUX_IN visibility - making it the only option capable of supporting adaptive, multi-mode CPU voltage management in modern mobile and server platforms.

Availability

PCA9561PW,112 is available at Aetrix Electronics and suitable for laptop SpeedStep implementation, server VRM interface design, and telecom baseband power management requiring stable component supply and long-term obsolescence planning.

Supply support for PCA9561PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The PCA9561PW,112 belongs to NXP's I²C-bus configurable logic and interface product line, designed specifically to replace mechanical DIP switches in CPU voltage identification and system configuration circuits.

FAQ

What is the primary function of the PCA9561PW,112 in CPU voltage regulation?

The PCA9561PW,112 serves as a programmable VID translator between the CPU and Voltage Regulator Module (VRM). It selects from four non-volatile EEPROM registers or six hardware inputs to drive the VRM's VID pins, enabling precise, software-controlled CPU voltage configuration for performance scaling or power conservation. Its operation is fully defined in the PCA9561PW,112 datasheet Section 6.5.

How does the MUX_SELECT pin interact with I²C-bus control in the PCA9561PW,112?

The MUX_SELECT pin determines whether MUX_OUT outputs reflect EEPROM register contents (logic 0) or MUX_IN hardware inputs (logic 1). However, the PCA9561PW,112 allows I²C-bus commands to override this pin - writing specific command bytes forces EEPROM sourcing regardless of MUX_SELECT state. This behavior is documented in Table 5 of the PCA9561PW,112 datasheet.

What voltage levels are supported on the MUX_IN and MUX_OUT pins of the PCA9561PW,112?

The MUX_IN_A–F and MUX_OUT_A–F pins of the PCA9561PW,112 are 5 V and 2.5 V tolerant, meaning they accept input signals up to 5.5 V and can interface safely with 2.5 V logic families without level-shifting. This tolerance is specified in Table 13 (Recommended Operating Conditions) and Table 15 (Static Characteristics) of the PCA9561PW,112 datasheet.

Can the PCA9561PW,112 be used with multiple devices on the same I²C-bus?

Yes - the PCA9561PW,112 features two hardware address pins (A0 and A1), allowing up to four devices to share the same I²C-bus. Each device responds to a unique 7-bit slave address (10011xx), as shown in Figure 3 of the PCA9561PW,112 datasheet. No additional address decoding logic is required.

What happens to the MUX_OUT outputs during power-up of the PCA9561PW,112?

At power-on, the PCA9561PW,112 performs an internal Power-On Reset (POR). If MUX_SELECT is logic 0, MUX_OUT outputs default to EEPROM byte 0 values; if MUX_SELECT is logic 1, they reflect current MUX_IN_A–F states. The POR threshold is 2.3–2.7 V (VPOR), and outputs remain stable only after VDD exceeds this range - details are in Section 6.5 of the PCA9561PW,112 datasheet.