My Inquiry
My Account
NXP Semiconductors PCA9704PW/Q900J
- Part No.:
- PCA9704PW/Q900J
- Manufacturer:
- NXP Semiconductors
- Category:
- I/O Expanders
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PCA9704PW/Q900J.pdf
- Description:
- IC XPNDR 5MHZ SPI 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,267
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PCA9704PW/Q900J from NXP Semiconductors is an AEC-Q100 qualified 8-bit SPI General Purpose Input (GPI) shift register with maskable interrupt output, 18 V tolerant inputs (with ≥100 kΩ series resistor), 4.5–5.5 V supply range, and ultra-low 2.5 µA max IDD - used for automotive body control module switch monitoring under harsh battery transients including 40 V load dump.
For engineers reviewing the PCA9704PW/Q900J datasheet, PCA9704PW/Q900J pinout, PCA9704PW/Q900J application, or PCA9704PW/Q900J equivalent, this page delivers verified electrical parameters, TSSOP16 pin mapping, daisy-chain SPI timing constraints, interrupt masking behavior, and automotive-grade design-in guidance for cyclic biasing and SBC wake extension.
Technical Context
The PCA9704PW/Q900J implements an 8-bit parallel input status register sampled on CS falling edge, loaded into a serial shift register on first SCLK rising edge, and shifted out via SDOUT with MSB-first SPI protocol. Its interrupt logic asserts INT (open-drain, active LOW) only when unmasked GPI state changes occur while INT_EN = HIGH.
Input tolerance relies on internal 18 V breakdown ESD protection plus external ≥100 kΩ series resistors to handle 27 V jump start and 40 V load dump; input thresholds are VIL ≤ 0.55×VDD (min 2.5 V at 4.5 V) and VIH ≥ 0.8×VDD, with 180 mV hysteresis at VDD = 4.5 V. All registers retain state down to VDD = 2.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDD Range | 4.5 V to 5.5 V - supports standard automotive 5 V rail with ±10% tolerance; power-on reset triggers below 2.2 V. |
| Input Voltage Tolerance | 18 V with ≥100 kΩ series resistor - enables direct connection to 12 V battery nodes during double-battery, reverse-battery, and 40 V load-dump events. |
| SPI Clock Speed | Up to 5 MHz - allows fast polling of 8 GPI states in <2 µs per read cycle; compatible with MCU SPI peripherals without clock division. |
| Supply Current (IDD) | Max 2.5 µA at VDD = 5.5 V - enables always-on switch monitoring in low-power ECU standby modes without compromising battery life. |
| Interrupt Output | Open-drain, active LOW - supports wired-AND daisy-chaining of multiple PCA9704PW/Q900J devices to single pull-up; requires ~10 kΩ external resistor. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive environments and industrial control cabinets without derating. |
| ESD Protection | ≥5 kV HBM, ≥1000 V CDM - exceeds AEC-Q100 stress requirements for assembly and field operation in vehicle harnesses. |
Pinout & Package
TSSOP16 package (SOT403-1), 4.4 mm body width, 0.65 mm pitch - surface-mount compatible with standard reflow profiles and automotive board space constraints.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SDOUT (Pin 1) | 3-state serial data output | Drives high-impedance when CS = HIGH; outputs MSB first on rising SCLK edges after CS goes LOW. |
| INT (Pin 2) | Open-drain interrupt output | Asserts LOW when unmasked GPI state change occurs; requires external 10 kΩ pull-up; supports wired-AND with other PCA9704 devices. |
| INT_EN (Pin 3) | Active-HIGH enable input | Enables GPI inputs and INT output when HIGH; disables both and places INT in high-Z when LOW - critical for cyclic biasing in SBC wake extensions. |
| IN0–IN7 (Pins 4–7, 9–12) | General purpose input ports | 18 V tolerant with ≥100 kΩ series resistor; VIL ≤ 2.5 V (at 4.5 V), VIH ≥ 3.6 V (at 4.5 V); hysteresis ≥180 mV prevents noise-induced toggling. |
| VSS (Pin 8) | Ground supply | Reference for all input thresholds and internal logic; must be low-impedance path to system ground plane. |
| CS (Pin 13) | Active-LOW chip select | Falling edge captures current GPI states into input status register and clears pending interrupt; rising edge stores new interrupt mask. |
| SCLK (Pin 14) | Serial clock input | Rising edge shifts data out of SDOUT and loads shift register; falling edge samples SDIN - defines full-duplex SPI timing window. |
| SDIN (Pin 15) | Serial data input | 20 µA internal pull-down prevents floating node in daisy-chain configurations; sampled on SCLK falling edge. |
| VDD (Pin 16) | Supply voltage | 4.5–5.5 V nominal; powers internal logic, ESD clamps, and input comparators; decoupling capacitor required within 1 cm. |
Key Features
| Feature | Design Value |
|---|---|
| 8-channel 18 V tolerant GPI | Each IN0–IN7 accepts up to 18 V via ≥100 kΩ resistor - eliminates need for external level-shifters in 12 V automotive switch monitoring. |
| Maskable interrupt generation | Software-configurable 8-bit mask register disables interrupt assertion per input - enables selective wake-up in multi-switch systems without MCU polling overhead. |
| Ultra-low standby current | 2.5 µA max IDD at 5.5 V - allows continuous monitoring in ECU stop-mode while maintaining <10 µA total system standby current. |
| Daisy-chain SPI interface | SDOUT-to-SDIN cascading supports unlimited GPI expansion - one CS/SCLK pair controls multiple PCA9704PW/Q900J devices with shared interrupt line. |
| AEC-Q100 Grade 1 compliance | Qualified for −40 °C to +125 °C operation with full PPAP documentation available - meets OEM requirements for body electronics and junction box modules. |
Applications
| Body Control Module (BCM) Switch Monitoring | SBC Wake Port Extension |
|---|---|
|
Use Scenario: Monitoring door lock/unlock, trunk release, and hazard light switches in modern BCMs exposed to 40 V load dump transients. IC Role / Device Role / Timing Role: GPI shift register capturing switch states via 100 kΩ-resistor-biased inputs; generates interrupt only on unmasked transitions to reduce MCU wake frequency. Use Value: Eliminates discrete voltage dividers and Schmitt triggers while sustaining AEC-Q100 reliability - reduces BOM count by 3+ components per 8-switch group. |
Use Scenario: Extending wake-capable inputs on UJA106x/UJA107xA System Basis Chips for low-power ECU standby with cyclic biasing. IC Role / Device Role / Timing Role: Secondary wake monitor enabled by SBC's V2/V3/WBIAS pins; INT_EN synchronized to bias cycles to avoid false interrupts during voltage settling. Use Value: Adds 8 reliable wake inputs per PCA9704PW/Q900J without increasing SBC pin count or requiring additional microcontroller GPIOs. |
| Industrial Emergency Lighting Control | Automotive Seat/Mirror Switch Interface |
|
Use Scenario: Detecting manual override switches in emergency exit lighting systems operating across −40 °C to +85 °C ambient with 24 V DC supply. IC Role / Device Role / Timing Role: SPI-accessible GPI with open-drain INT tied to PLC input; tolerates 27 V jump-start surges during generator backup activation. Use Value: Enables single-board integration of switch sensing and surge protection - avoids separate TVS arrays and optocouplers in Class I hazardous location designs. |
Use Scenario: Reading position-memory switches for power seats and mirrors in premium vehicles where EMI immunity and long-term contact reliability are critical. IC Role / Device Role / Timing Role: High-immunity GPI with 180 mV hysteresis and 5 kV HBM ESD rating - rejects cable harness noise while detecting slow-contact bounce. Use Value: Reduces switch debouncing firmware complexity and eliminates external RC filters - improves time-to-first-read accuracy by >30% versus discrete solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit SPI GPI applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX7315ATL+ | 5 V only, 12 V input tolerant (not 18 V), no interrupt masking, 10 µA IDD | Lacks AEC-Q100 qualification and 40 V load dump support; suitable for non-automotive industrial use | Select only if 18 V tolerance and automotive qualification are not required; verify external ESD protection for 27 V transients. |
| TCA9534APWR | I²C interface (not SPI), 6 V max VDD, 5.5 V input tolerant, no interrupt masking, 1 µA IDD | Requires I²C host; incompatible with SPI-only microcontrollers; no automotive qualification | Choose only for I²C-based systems needing lower quiescent current; cannot replace PCA9704PW/Q900J in SPI or high-voltage automotive contexts. |
Compared with MAX7315ATL+ and TCA9534APWR, the PCA9704PW/Q900J uniquely combines 18 V input tolerance, SPI daisy-chaining, maskable interrupt, and AEC-Q100 Grade 1 - making it the sole option for cost-sensitive, high-reliability automotive switch monitoring where voltage transients and interrupt granularity are design-critical.
Availability
PCA9704PW/Q900J is available at Aetrix Electronics and suitable for automotive body control modules, industrial emergency lighting systems, and SBC wake port extensions requiring stable component supply across extended temperature ranges and harsh electrical environments.
Supply support for PCA9704PW/Q900J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in AEC-Q100-qualified interface ICs.
The PCA9704PW/Q900J belongs to NXP's automotive-grade GPI portfolio designed specifically for robust switch monitoring in body electronics, enabling reliable wake-up signaling and transient-hardened input acquisition in modern vehicle ECUs.
FAQ
What is the maximum input voltage the PCA9704PW/Q900J can tolerate on its IN0–IN7 pins?
The PCA9704PW/Q900J supports up to 18 V on IN0–IN7 when used with a minimum 100 kΩ external series resistor. This enables operation during automotive transients including 27 V jump start and 40 V load dump. Without the resistor, absolute maximum input voltage is 6 V per the datasheet limiting values table.
Does the PCA9704PW/Q900J require external pull-up resistors on its interrupt output?
Yes, the PCA9704PW/Q900J features an open-drain INT output that requires an external pull-up resistor - typically 10 kΩ to VDD - to assert a valid HIGH level. This configuration enables wired-AND daisy-chaining of multiple PCA9704PW/Q900J devices onto a single interrupt line.
How does the interrupt masking feature work in the PCA9704PW/Q900J?
The PCA9704PW/Q900J uses an 8-bit interrupt mask register loaded via SPI. A mask bit = 0 disables interrupt generation for the corresponding input (IN0–IN7); a mask bit = 1 enables it. The mask must be correctly aligned in the shift register before CS rising edge - misalignment causes unintended interrupt behavior.
Is the PCA9704PW/Q900J pin-compatible with other NXP GPI devices like the PCA9701 or PCA9702?
No, the PCA9704PW/Q900J is not pin-compatible with PCA9701 or PCA9702. It uses a dedicated 16-pin TSSOP layout with unique pin assignments including SDIN pull-down, INT_EN enable, and daisy-chain SDOUT/SDIN routing - confirmed by Figure 2 and Table 3 in the official datasheet.
What is the role of the INT_EN pin in power-constrained automotive applications?
In power-constrained automotive applications, the INT_EN pin enables precise control of PCA9704PW/Q900J power state: when LOW, it disables GPI inputs and places INT in high-impedance, reducing system leakage; when HIGH, it activates both - allowing synchronization with SBC cyclic biasing to minimize total ECU standby current.
PCA9704PW/Q900J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Number of I/O:
- 8 (Input Only)
- Interface:
- SPI
- Interrupt Output:
- Yes
- Features:
- -
- Output Type:
- Open Drain
- Current - Output Source/Sink:
- -
- Clock Frequency:
- 5 MHz
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
PCA9704PW/Q900J FAQ
1.How can I place an order for PCA9704PW/Q900J through Aetrix?
Please submit a Request for Quotation (RFQ) for PCA9704PW/Q900J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PCA9704PW/Q900J reliable?
The price and inventory of PCA9704PW/Q900J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PCA9704PW/Q900J is usually 5 days.
3.What payment methods are accepted for PCA9704PW/Q900J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PCA9704PW/Q900J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PCA9704PW/Q900J?
PCA9704PW/Q900J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PCA9704PW/Q900J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PCA9704PW/Q900J?
For technical support, including PCA9704PW/Q900J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PCA9704PW/Q900J requirements.
6.How does Aetrix verify that PCA9704PW/Q900J is sourced from the original manufacturer or authorized distributors?
All PCA9704PW/Q900J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PCA9704PW/Q900J meets industry standards.
7.What is the process for return or replacement of PCA9704PW/Q900J?
All PCA9704PW/Q900J units undergo pre-shipment inspection (PSI). If there is an issue with PCA9704PW/Q900J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PCA9704PW/Q900J part is unused and in its original packaging.
Return procedure for PCA9704PW/Q900J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PCA9704PW/Q900J Tags
-
TCA6408ARSVR
Texas Instruments
-
TCA9535RTWR
Texas Instruments
-
FXL6408UMX
onsemi
-
PCF8574ADWR
Texas Instruments
-
PCF8574APWR
Texas Instruments
-
TCA9555PWR
Texas Instruments
-
TCA9554PWR
Texas Instruments
-
TCA9554APWR
Texas Instruments
-
TCA9539PWR
Texas Instruments
-
TCA9534PWR
Texas Instruments
-
TCA9555RTWR
Texas Instruments
-
TCA9535PWR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
