NXP Semiconductors PCAL6524HEAZ

Overview

PCAL6524HEAZ from NXP Semiconductors is a 24-bit ultra low-voltage I²C-bus/SMBus I/O expander with Agile I/O features, interrupt output, and hardware/software reset. It provides bidirectional voltage-level translation between 0.8 V–3.6 V I²C-bus and 1.8 V–5.5 V port-side I/Os, supports 1 MHz Fm+ operation, and delivers 25 mA sink per port pin for direct LED driving - used in battery-powered mobile sensor interfaces and mixed-voltage microcontroller systems.

For engineers reviewing the PCAL6524HEAZ datasheet, PCAL6524HEAZ pinout, PCAL6524HEAZ application, or PCAL6524HEAZ equivalent, this page delivers verified technical context, real-world design meaning of key specs (e.g., dual-supply operation, per-pin interrupt edge control, switch debounce hardware), and validated alternative options for remote GPIO expansion in space-constrained, low-power embedded designs.

Technical Context

The PCAL6524HEAZ implements a dual-supply architecture: VDD(I2C-bus) (0.8 V–3.6 V) sets I²C interface voltage and enables bidirectional level shifting, while VDD(P) (1.8 V–5.5 V) powers the 24-bit I/O port and core logic. Its Agile I/O engine supports per-pin configuration of output drive strength, pull-up/pull-down enable and selection (100 kΩ), latchable inputs, and open-drain/push-pull mode.

Interrupt functionality includes bit-wise edge/level specification, individual interrupt clear without disturbing other pending events, interrupt status register read, and hardware switch debounce with programmable count. The device also supports I²C software reset (general call 00h + 06h) and device ID read (F8h/F9h) for system identification and recovery.

Key Specifications

Pinout & Package

PCAL6524HEAZ is packaged in a 5 × 5 × 0.56 mm HUQFN32 (SOT1426-1) with wettable flanks, optimized for automated optical inspection and high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O expansion applications.

Compared with TCA6424A and PCA9539, PCAL6524HEAZ uniquely supports 0.8 V I²C operation, per-pin Agile I/O configuration, integrated switch debounce, and bit-wise interrupt control - making it the only option for energy-constrained, mixed-voltage, and high-reliability remote I/O applications.

Availability

PCAL6524HEAZ is available at Aetrix Electronics and suitable for battery-powered wearables, IoT sensor hubs, portable instrumentation, and industrial control modules requiring stable component supply across extended temperature ranges (−40 °C to +85 °C).

Supply support for PCAL6524HEAZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in interface and power management ICs.

The PCAL6524HEAZ belongs to NXP's Agile I/O expander product line, engineered specifically for low-power, mixed-voltage embedded systems needing intelligent, software-configurable remote GPIO with minimal external components.

FAQ

What is the minimum VDD(I2C-bus) voltage supported by PCAL6524HEAZ?

The PCAL6524HEAZ supports VDD(I2C-bus) down to 0.8 V, enabling direct interface with ultra-low-voltage microcontrollers such as ARM Cortex-M0+ derivatives operating in deep-sleep modes. This capability is confirmed in Section 2 of the datasheet and is critical for extending battery life in portable devices. The 0.8 V threshold is guaranteed across the full −40 °C to +85 °C temperature range, and the I²C interface remains fully compliant with Fast-Mode Plus timing at this voltage.

Does PCAL6524HEAZ support hardware debounce for mechanical switches?

Yes, PCAL6524HEAZ includes dedicated hardware switch debounce circuitry controlled via registers 74h (debounce enable 0), 75h (debounce enable 1), and 76h (debounce count). This feature eliminates the need for firmware-based timing loops or external RC filters. Each port group (P0, P1, P2) can be independently enabled for debounce, and the debounce window is programmable - allowing precise rejection of contact bounce without affecting response latency for valid transitions.

How many I²C addresses can be assigned to PCAL6524HEAZ using the ADDR pin?

The ADDR pin on PCAL6524HEAZ allows selection of one of four unique I²C target addresses: 40h, 42h, 44h, or 46h - depending on whether ADDR is tied to SCL, SDA, VSS, or VDD(I2C-bus), respectively. This enables up to four PCAL6524HEAZ devices to share the same I²C bus without address conflict. The mapping is defined in Table 4 of the datasheet and applies identically to all variants including PCAL6524HEAZ.

Can PCAL6524HEAZ drive LEDs directly, and what is its maximum sink current per pin?

Yes, PCAL6524HEAZ can drive LEDs directly with a guaranteed 25 mA sink current per I/O pin (P0_0–P2_7), as specified in Section 2 Features and Benefits. This eliminates the need for external transistor drivers in status indicator applications. The output stage supports both push-pull and open-drain configurations, and drive strength is programmable to optimize rise/fall times and EMI in low-capacitance layouts - all configurable per pin via Agile I/O registers.

What is the purpose of the two separate supply pins VDD(I2C-bus) and VDD(P) on PCAL6524HEAZ?

VDD(I2C-bus) powers the I²C interface circuitry and defines the logic threshold for SCL/SDA (0.8–3.6 V), while VDD(P) powers the 24-bit I/O port and internal core logic (1.8–5.5 V). This dual-supply architecture enables true bidirectional voltage-level translation: the PCAL6524HEAZ can communicate with a 0.8 V microcontroller over I²C while simultaneously interfacing with 5 V sensors or actuators on its port pins - all without external level shifters or voltage translators.