NXP Semiconductors PCAL9722HNHP

Overview

PCAL9722HNHP from NXP Semiconductors is a 22-bit ultra low-voltage SPI I/O expander with bidirectional level translation, Agile I/O features, active-low interrupt output, and hardware reset. It operates with VDD(SPI) down to 1.1 V and VDD(P) from 1.8 V to 5.5 V, supports 5 MHz SPI clock, and delivers 25 mA sink per port pin for direct LED driving. It enables remote GPIO expansion in battery-powered microcontroller systems requiring mixed-voltage interoperation.

For engineers reviewing the PCAL9722HNHP datasheet, PCAL9722HNHP pinout, PCAL9722HNHP application, or PCAL9722HNHP equivalent, this page provides verified technical context, validated pin functions, confirmed voltage translation behavior, real-world use cases, and two rigorously cross-checked alternative parts for system-level design continuity.

Technical Context

The PCAL9722HNHP implements dual-supply architecture: VDD(SPI) sets the logic threshold for SPI interface (1.1–5.5 V) and enables bidirectional level shifting, while VDD(P) powers Port P (1.8–5.5 V) and defines output drive voltage. Its Agile I/O engine supports per-pin configuration of pull-up/pull-down (100 kΩ), output drive strength (4 levels), latchable inputs, and interrupt edge/level selection.

Interrupt logic includes maskable per-pin events, individual clear capability without disturbing other pending interrupts, and hardware switch debounce. The device uses an auto-increment pointer register for sequential register access and features dedicated registers for polarity inversion, input status, and interrupt status-enabling deterministic host-side event handling without polling overhead.

Key Specifications

Pinout & Package

Package: HVQFN32 (5 mm × 5 mm × 0.85 mm, 0.5 mm pitch, wettable flank). Thermal-enhanced plastic package with exposed thermal pad for improved power dissipation in compact layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O expansion applications.

Compared with PCA9539DWR and MAX7317ATL+, the PCAL9722HNHP uniquely supports true 1.1 V–5.5 V bidirectional translation, per-pin Agile I/O configurability, and hardware debounce - delivering measurable reduction in firmware development time and external component count for mixed-voltage embedded systems.

Availability

PCAL9722HNHP is available at Aetrix Electronics and suitable for smart wearables, industrial HMIs, automotive cabin controls, and medical portable monitors requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PCAL9722HNHP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in mixed-signal and low-power interface ICs.

The PCAL9722HNHP belongs to NXP's Agile I/O family, designed specifically to simplify remote GPIO expansion in energy-constrained, mixed-voltage embedded systems where software overhead and board space must be minimized.

FAQ

What is the function of the ADDR pin on the PCAL9722HNHP?

The ADDR pin on the PCAL9722HNHP selects one of two SPI target addresses: connecting ADDR to VSS sets the address to 40h, while connecting it to VDD(SPI) sets it to 42h. This enables two PCAL9722HNHP devices to share the same SPI bus without address conflict. The PCAL9722HNHP uses this pin exclusively for address configuration - it has no effect on internal register behavior or power sequencing.

Does the PCAL9722HNHP support true bidirectional level translation between different voltage domains?

Yes, the PCAL9722HNHP supports true bidirectional level translation via its dual-supply architecture: VDD(SPI) defines the logic threshold for the SPI interface (1.1–5.5 V), while VDD(P) sets the output voltage and sink capability for the 22 I/O pins (1.8–5.5 V). This allows a 1.2 V microcontroller to communicate with 5 V peripherals without external translators - a capability confirmed in Section 1 and Figure 1 of the official datasheet.

How does the PCAL9722HNHP handle interrupt events from fast-moving inputs?

The PCAL9722HNHP uses input latch registers (48h–4Ah) to hold the logic state that triggered an interrupt until the corresponding input port register is read. This prevents missed events during host ISR execution. Combined with individual interrupt clear registers (68h–6Ah), the PCAL9722HNHP ensures deterministic, low-latency response to fast transitions - a feature explicitly documented in Sections 2.2 and 6.4.6 of the datasheet.

Can the PCAL9722HNHP directly drive LEDs, and what is the maximum current per pin?

Yes, the PCAL9722HNHP can directly drive LEDs with up to 25 mA sink current per I/O pin (P0_0–P2_5), as specified in Section 2 and Table 24 of the datasheet. This eliminates the need for external driver transistors in most indicator applications. Drive strength is programmable in four levels, allowing optimization for brightness, power, and EMI - a capability unique to the Agile I/O feature set of the PCAL9722HNHP.

What is the power-on reset behavior of the PCAL9722HNHP, and how does it differ from the RESET pin assertion?

At power-on, the PCAL9722HNHP initializes all registers to their default states and resets the SPI state machine - identical to asserting the active-low RESET pin. Both actions restore configuration registers (e.g., all I/Os as inputs), output registers (all high), and interrupt logic to known conditions. The RESET pin provides a synchronous, software-controllable recovery path without cycling VDD(P) or VDD(SPI), as detailed in Section 1 and Table 6 of the datasheet.