NXP Semiconductors PCAL9722HN/Q900HP
- Part No.:
- PCAL9722HN/Q900HP
- Manufacturer:
- NXP Semiconductors
- Category:
- I/O Expanders
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
PCAL9722HN/Q900HP.pdf
- Description:
- PCAL9722HN/Q900
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PCAL9722HN/Q900HP from NXP Semiconductors is a 22-bit ultra low-voltage SPI I/O expander with bidirectional level translation (1.1 V to 5.5 V on SPI side, 1.8–5.5 V on port side), 5 MHz SCLK support, 25 mA sink capability per port pin, and integrated Agile I/O features including programmable drive strength, input latching, and hardware switch debounce. It serves as a remote GPIO extension for low-power microcontrollers in space-constrained industrial and automotive systems.
For engineers reviewing the PCAL9722HN/Q900HP datasheet, PCAL9722HN/Q900HP pinout, PCAL9722HN/Q900HP application, or PCAL9722HN/Q900HP equivalent, this page delivers verified technical context, real-world use cases, validated alternatives, and supply-ready procurement details - all grounded in NXP's Rev. 1.2 product data sheet dated 3 July 2025.
Technical Context
The PCAL9722HN/Q900HP implements dual-supply architecture with independent VDD(SPI) (1.1–5.5 V) and VDD(P) (1.8–5.5 V), enabling true bidirectional voltage translation without external level shifters. Its SPI interface operates up to 5 MHz with Schmitt-triggered inputs (Vhys = 0.11 V at 1.1 V) and integrated noise filtering on SCLK, SDIN, and CS.
Agile I/O functionality includes per-pin configuration of push-pull/open-drain outputs, four-level programmable drive strength, bit-wise interrupt masking and edge/level specification, individual interrupt clear, and dedicated hardware switch debounce (configurable count and enable). All 22 I/Os default to high-impedance inputs at power-on reset.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| SPI Clock Speed | Up to 5 MHz - enables fast register access and real-time GPIO updates in latency-sensitive control loops. |
| VDD(SPI) Range | 1.1 V to 5.5 V - supports direct interfacing with next-gen sub-1.2 V microcontrollers while maintaining robust noise immunity. |
| VDD(P) Range | 1.8 V to 5.5 V - powers port-side peripherals (e.g., 3.3 V sensors or 5 V LEDs) independently of controller voltage. |
| I/O Count & Type | 22 programmable I/Os across three ports (P0_0–P0_7, P1_0–P1_7, P2_0–P2_5) - provides flexible bank- or pin-level direction and drive control. |
| Interrupt Output | Open-drain active-low INT with maskable per-pin edge/level detection and latch-hold - eliminates polling and reduces host CPU wake-up latency. |
| Standby Current | 2.0 μA typical at 3.3 V - extends battery life in always-on sensor nodes and portable equipment. |
| ESD Protection | 2000 V HBM, 1000 V CDM - ensures reliability in handling-sensitive manufacturing and field-repair environments. |
Pinout & Package
PCAL9722HN/Q900HP uses the HVQFN32 (SOT617-3) package: 5 mm × 5 mm × 0.85 mm body, 0.5 mm pitch, thermal-enhanced wettable flank, 32 terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SCLK (29) | SPI clock input | Accepts up to 5 MHz clock; Schmitt-triggered for slow-edge/noise resilience. |
| SDIN (30) | SPI data input | Receives command/address bytes; filtered for EMI robustness. |
| SDOUT (24) | SPI data output | Drives read-back data; synchronized to SCLK falling edge. |
| CS (23) | Chip select input | Active-low enable; initiates SPI transaction and auto-increment pointer mode. |
| INT (32) | Interrupt output | Open-drain, active-low signal indicating changed input state or edge event; requires external pull-up. |
| RESET (28) | Active-low reset input | Hardware-initiated initialization; resets registers and SPI state machine without power cycle. |
| ADDR (26) | Address configuration | Binary-selects SPI target address (40h or 42h); enables dual-device bus sharing. |
| VDD(SPI) (31) | SPI interface supply | Sets logic threshold and enables level translation; must match controller VDD. |
| VDD(P) (27) | Port-side supply | Determines output high-level voltage and sink/source capability for all 22 I/Os. |
| VSS (25) | Ground reference | Common return for both SPI and port domains; critical for noise isolation. |
| P0_0–P0_7 (1–8) | Port 0 I/Os | 8-bit general-purpose pins with configurable drive, pull, latch, and interrupt behavior. |
| P1_0–P1_7 (9–16) | Port 1 I/Os | 8-bit general-purpose pins supporting identical Agile I/O features as Port 0. |
| P2_0–P2_5 (17–22) | Port 2 I/Os | 6-bit general-purpose pins with full feature set, including switch debounce enable. |
Key Features
| Feature | Design Value |
|---|---|
| Per-pin Agile I/O configuration | Independent selection of push-pull/open-drain output, 4-level drive strength, and pull-up/pull-down enable per I/O - eliminates discrete bias components and optimizes signal integrity. |
| Hardware switch debounce | Dedicated debounce logic per port with programmable enable and 8-bit counter - removes firmware overhead and prevents false triggers in mechanical keypads or limit switches. |
| Latched input capture | Input state held until register read - ensures no interrupt event is lost during host servicing, critical for fast-changing signals like encoder quadrature or pulse-width inputs. |
| Bit-wise interrupt control | Individual mask, edge/level select, and clear per pin - enables selective event monitoring without disabling other interrupts or disturbing pending status. |
| Dual-supply level translation | VDD(SPI) and VDD(P) decoupled supplies allow seamless interoperation between 1.1 V MCUs and 5 V peripherals - removes need for external translators in mixed-voltage systems. |
Applications
| Industrial Human-Machine Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Keypad, rotary encoder, and LED indicator interface in panel-mounted controllers with space-constrained PCB layout. IC Role / Device Role / Timing Role: Remote GPIO extender translating 1.2 V MCU SPI to 3.3 V/5 V peripheral logic levels; provides debounced input capture and 25 mA LED drive. Use Value: Reduces BOM count by eliminating discrete level shifters, pull resistors, and debounce timers while enabling direct LED driving without external drivers. |
Use Scenario: Door module sensing (window switch, lock actuator feedback) and interior lighting control in AEC-Q100 Grade 1 environments. IC Role / Device Role / Timing Role: Automotive-qualified I/O expander with -40 °C to +125 °C operation, hardware reset, and ESD-hardened I/Os for reliable cabin subsystem interfacing. Use Value: Meets automotive qualification requirements out-of-box; eliminates software debounce routines and simplifies ASIL-B–compatible diagnostics via interrupt status registers. |
| Portable Medical Sensor Hub | Smart Energy Meter Interface |
|
Use Scenario: Battery-powered wearable device aggregating biometric sensor inputs (PPG, temperature) and user controls under strict power budget. IC Role / Device Role / Timing Role: Ultra-low standby current (2.0 μA) I/O expander with interrupt-driven wake-up; supports 1.1 V MCU sleep modes and 3.3 V sensor interfaces. Use Value: Extends battery life by >30% versus polling-based GPIO expansion; enables precise timing-critical sampling via latched input capture. |
Use Scenario: Tamper detection, relay driver interface, and LCD segment control in utility-grade electricity meters requiring long-term reliability. IC Role / Device Role / Timing Role: Robust 22-bit I/O hub with 5.5 V tolerant pins, latch-up immunity (>100 mA), and programmable drive strength for driving relays and LCD backlights. Use Value: Replaces multiple discrete interface ICs; withstands harsh metering environments with certified ESD and latch-up performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar I/O expansion applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PCA9539RPW | 16-bit I²C expander; no level translation; fixed 2.3–5.5 V VDD; no Agile I/O features (no drive strength, debounce, or per-pin interrupt control) | Limited to I²C systems; unsuitable for ultra-low-voltage (<1.2 V) controllers or mixed-voltage designs requiring translation | Select when I²C is mandated and voltage compatibility is guaranteed across all connected devices. |
| TCA6424ARGTR | 24-bit I²C expander with level translation (1.65–3.6 V I²C, 1.65–5.5 V port); no hardware debounce; no per-pin edge/level interrupt config | Requires I²C bus; lacks interrupt individual clear and switch debounce - increases firmware complexity for mechanical inputs | Choose for higher I/O count where I²C bandwidth suffices and debounce is handled in software. |
Compared with PCA9539RPW and TCA6424ARGTR, PCAL9722HN/Q900HP uniquely combines SPI interface, sub-1.2 V compatibility, per-pin Agile I/O control, and integrated hardware debounce - making it the only option for high-reliability, low-power, mixed-voltage systems demanding minimal firmware overhead.
Availability
PCAL9722HN/Q900HP is available at Aetrix Electronics and suitable for automotive body control modules, industrial HMI panels, portable medical sensor hubs, and smart energy meter interfaces requiring stable component supply across extended temperature and qualification requirements.
Supply support for PCAL9722HN/Q900HP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in mixed-signal interface ICs and automotive-grade qualification.
The PCAL9722HN/Q900HP belongs to NXP's Agile I/O family, designed specifically to simplify GPIO expansion in heterogeneous voltage systems while reducing firmware complexity through hardware-accelerated features like debounce, latching, and per-pin interrupt control.
FAQ
What is the operating temperature range for PCAL9722HN/Q900HP?
PCAL9722HN/Q900HP is rated for –40 °C to +125 °C ambient operation and is AEC-Q100 Grade 1 qualified, making it suitable for under-hood automotive applications and industrial environments with wide thermal excursions. This extended range is confirmed in Table 2 of the official NXP datasheet Rev. 1.2.
Does PCAL9722HN/Q900HP support true bidirectional level translation?
Yes, PCAL9722HN/Q900HP implements true bidirectional level translation using separate VDD(SPI) and VDD(P) supplies. VDD(SPI) sets the SPI interface logic thresholds (1.1–5.5 V), while VDD(P) defines port-side output levels (1.8–5.5 V), enabling simultaneous communication between sub-1.2 V microcontrollers and 5 V peripherals without external translators.
How does the hardware switch debounce function in PCAL9722HN/Q900HP?
PCAL9722HN/Q900HP includes dedicated hardware debounce logic per port, controlled by Switch Debounce Enable (74h–75h) and Debounce Count (76h) registers. When enabled, it filters mechanical switch bounce using a programmable 8-bit counter, eliminating the need for software polling or timer-based debounce routines in the host MCU.
Can PCAL9722HN/Q900HP drive LEDs directly?
Yes, PCAL9722HN/Q900HP supports 25 mA sink current per port pin, allowing direct LED driving without external current-limiting transistors. Its programmable output drive strength and open-drain/push-pull configuration provide flexibility for varying LED forward voltages and brightness requirements.
What is the purpose of the ADDR pin on PCAL9722HN/Q900HP?
The ADDR pin on PCAL9722HN/Q900HP selects between two SPI target addresses (40h or 42h), enabling up to two PCAL9722HN/Q900HP devices to share the same SPI bus without address conflict. This simplifies multi-node I/O expansion in compact systems where board space limits additional chip selects.
PCAL9722HN/Q900HP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Number of I/O:
- -
- Interface:
- -
- Interrupt Output:
- -
- Features:
- -
- Output Type:
- -
- Current - Output Source/Sink:
- -
- Clock Frequency:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
PCAL9722HN/Q900HP FAQ
1.How can I place an order for PCAL9722HN/Q900HP through Aetrix?
Please submit a Request for Quotation (RFQ) for PCAL9722HN/Q900HP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PCAL9722HN/Q900HP reliable?
The price and inventory of PCAL9722HN/Q900HP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PCAL9722HN/Q900HP is usually 5 days.
3.What payment methods are accepted for PCAL9722HN/Q900HP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PCAL9722HN/Q900HP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PCAL9722HN/Q900HP?
PCAL9722HN/Q900HP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PCAL9722HN/Q900HP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PCAL9722HN/Q900HP?
For technical support, including PCAL9722HN/Q900HP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PCAL9722HN/Q900HP requirements.
6.How does Aetrix verify that PCAL9722HN/Q900HP is sourced from the original manufacturer or authorized distributors?
All PCAL9722HN/Q900HP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PCAL9722HN/Q900HP meets industry standards.
7.What is the process for return or replacement of PCAL9722HN/Q900HP?
All PCAL9722HN/Q900HP units undergo pre-shipment inspection (PSI). If there is an issue with PCAL9722HN/Q900HP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PCAL9722HN/Q900HP part is unused and in its original packaging.
Return procedure for PCAL9722HN/Q900HP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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