NXP Semiconductors PCF8584T/2,518
- Part No.:
- PCF8584T/2,518
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
PCF8584T/2,518.pdf
- Description:
- IC CTRL PARALLEL/I2C BUS 20-SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PCF8584T/2,518 from NXP Semiconductors (formerly Philips) is a parallel-bus-to-I²C-bus protocol converter IC supporting both master and slave operation, with programmable SCL frequencies up to 90 kHz, −40 to +85 °C operating temperature range, and 4.5–5.5 V supply voltage. It interfaces 8051, Z80, 68000, and 8049 microcontrollers to I²C-bus systems in industrial control and embedded instrumentation.
For engineers reviewing the PCF8584T/2,518 datasheet, PCF8584T/2,518 pinout, PCF8584T/2,518 application, or PCF8584T/2,518 equivalent, key selection considerations include its dual-mode interface auto-detection (80XX/68000), long-distance 4-wire mode, monitor mode capability, interrupt vector programmability, and register-level control of START/STOP/ACK via S1.
Technical Context
The PCF8584T/2,518 implements full I²C-bus protocol handling-including arbitration, timing, START/STOP generation, ACK/NACK control, and multi-master conflict resolution-via dedicated internal logic and five mapped registers (S0–S3, S0′). Its parallel interface uses A0, WR/RW, RD/DTACK, CS, and RESET/STROBE to support asynchronous access across multiple CPU families.
It features three operational modes: standard 2-wire I²C-bus mode, 4-wire long-distance mode (requiring external line drivers), and passive monitor mode (enabled by zeroing S0′). Clock prescaling (S22–S24) adapts to input clock frequencies from 3 MHz to 12 MHz, while S20–S21 select one of four SCL output frequencies: 90 kHz, 45 kHz, 11 kHz, or 1.5 kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL/CMOS microcontroller buses without level-shifting. |
| Operating Temperature | −40 °C to +85 °C - supports deployment in industrial environments without derating. |
| Max SCL Frequency | 90 kHz - enables high-speed I²C communication for time-critical sensor or EEPROM access. |
| I²C Bus Role | Master and slave - allows bidirectional integration into mixed-role I²C networks (e.g., MCU as master, PCF8584T/2,518 as slave peripheral). |
| Parallel Interface | 8-bit bidirectional data bus (DB0–DB7) with mode-agnostic control (WR/RW, RD/DTACK, CS, A0) - eliminates need for bus-specific glue logic. |
| Interrupt Support | Programmable 8-bit vector (S3) with ENI-controlled open-drain INT output - enables direct integration with vectored-interrupt CPUs like 68000. |
| Special Modes | Monitor mode (S0′ = 00H), long-distance 4-wire mode (ES1=1, ESO=1), strobe mode (address+STOP triggers monostable pulse) - provides debug visibility, extended cabling, and bus arbitration signaling. |
Pinout & Package
PCF8584T/2,518 is housed in a plastic small outline package (SO20), 20-lead, 7.5 mm body width (SOT163-1), with gull-wing leads suitable for surface-mount reflow soldering per JEDEC standards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK | Clock input | Accepts microcontroller clock source (3–12 MHz); drives internal prescaler and digital filters for SCL/SDA timing stability. |
| SDA / SDA OUT | Serial data I/O | Open-drain bidirectional I²C data line; becomes unidirectional output in long-distance mode. |
| SCL / SCL IN | Serial clock I/O | Open-drain bidirectional I²C clock line; becomes unidirectional input in long-distance mode. |
| IACK / SDA IN | Interrupt acknowledge input | Triggers vector readout on DB0–DB7 when ENI=1; serves as serial data input in long-distance mode. |
| INT / SCL OUT | Interrupt output | Open-drain active-low interrupt signal; repurposed as serial clock output in long-distance mode. |
| A0 | Register select | High selects control/status register S1; low enables access to S0, S0′, S2, or S3 depending on ES1/ES2. |
| DB0–DB7 | Parallel data bus | 8-bit bidirectional port for register read/write; carries interrupt vector during IACK cycle. |
| RESET/STROBE | Reset input / strobe output | Active-low reset (≥30 CLK cycles); outputs 8-cycle monostable pulse on address+STOP in strobe mode. |
| CS | Chip select | Enables parallel bus access; used with WR/RW to auto-detect 80XX vs. 68000 interface mode. |
| WR (R/W) | Write control | Writes to registers when CS active; polarity and function adapt automatically to target CPU family. |
| RD (DTACK) | Read control | Reads registers or acknowledges data transfer; DTACK output in 68000 mode enables synchronous handshaking. |
| VDD, VSS | Power supply | 5 V supply and ground pins - decoupling required per CMOS layout guidelines to suppress switching noise on I²C lines. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-detect parallel interface mode | Identifies 80XX (8051/Z80) or 68000 bus timing on power-up using WR-CS sequence - eliminates manual configuration jumpers or firmware mode selection. |
| Programmable SCL frequency | Four selectable rates (90/45/11/1.5 kHz) via S20–S21, with clock prescaler (S22–S24) adapting to 3–12 MHz input clocks - ensures precise timing across diverse host oscillator sources. |
| Long-distance 4-wire mode | Reconfigures SDA/SCL pins as unidirectional SDA OUT, SCL IN, SDA IN, SCL OUT - enables RS-422/485-based extension beyond standard I²C 1 m limit. |
| Passive I²C bus monitor | Activated by writing 00H to S0′ - captures all I²C traffic without ACK generation or bus contention, ideal for protocol analysis and fault tracing. |
| Strobe output on address+STOP | Generates 8-clock-cycle active-low pulse at RESET/STROBE pin - provides hardware synchronization signal for multi-master parallel-bus arbitration. |
| Dual-register S0 architecture | Separate shift register (write-only) and read buffer (read-only) - prevents data corruption during concurrent transmit/receive operations and simplifies byte-handling firmware. |
Applications
| Industrial Sensor Hub | Legacy MCU I²C Bridge |
|---|---|
|
Use Scenario: Central controller (8051) aggregates data from multiple I²C temperature, pressure, and humidity sensors in factory-floor equipment. IC Role / Device Role / Timing Role: PCF8584T/2,518 acts as master controller, initiating reads, managing arbitration, and buffering sensor responses on the I²C bus. Use Value: Enables legacy 8-bit microcontrollers without native I²C peripherals to drive modern I²C sensor arrays with deterministic timing and error recovery (BER detection, LAB flag). |
Use Scenario: Retrofitting a Z80-based medical instrument with I²C EEPROM for calibration data storage. IC Role / Device Role / Timing Role: PCF8584T/2,518 operates as I²C slave, responding to Z80 writes/reads via its parallel interface while maintaining strict I²C timing compliance. Use Value: Eliminates need for custom FPGA or discrete logic; leverages existing Z80 bus timing and interrupt structure without modifying PCB layout or firmware architecture. |
| I²C Bus Monitor & Debugger | Multi-Master Industrial Network |
|
Use Scenario: Field technician diagnosing intermittent I²C communication failures in a PLC backplane. IC Role / Device Role / Timing Role: PCF8584T/2,518 runs in monitor mode (S0′ = 00H), passively capturing START/STOP, addresses, and data bytes without affecting bus timing. Use Value: Provides real-time visibility into I²C traffic including ACK/NACK status (LRB bit), arbitration loss (LAB), and bus errors (BER) - no bus interruption or additional pull-ups required. |
Use Scenario: Distributed control system where multiple 68000-based nodes share one I²C bus for shared memory and status reporting. IC Role / Device Role / Timing Role: Each PCF8584T/2,518 functions as multi-master node, detecting BB flag before transmission and asserting STO/STA under software control. Use Value: Hardware-enforced arbitration and automatic STOP/START chaining prevent bus lockup; strobe output synchronizes parallel-bus access across nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar I²C-bus controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PCA9564 | Successor IC with identical pinout, enhanced ESD rating (4 kV HBM), wider voltage range (2.7–5.5 V), and integrated clock generator (no external CLK required). | Supports lower-voltage hosts (e.g., 3.3 V ARM cores); eliminates external crystal/clock source; not drop-in compatible due to different reset behavior and S1 bit mapping. | Select PCA9564 for new designs requiring 3.3 V operation, higher robustness, or simplified BOM; retain PCF8584T/2,518 for legacy 5 V systems with existing CLK infrastructure. |
| PCF8584P | Same die, DIP20 package (SOT146-1) instead of SO20; identical electrical specs, timing, and register set. | Used in through-hole prototyping, repair, or legacy board upgrades where SOIC footprint is unavailable. | Choose PCF8584P only when mechanical constraints require DIP packaging; no functional difference - same firmware and schematic design applies. |
Compared with PCA9564, PCF8584T/2,518 requires an external clock source and operates strictly at 5 V, but offers proven field reliability in industrial 8051/Z80 systems; compared with PCF8584P, it delivers identical functionality in a space-saving SOIC package optimized for automated assembly.
Availability
PCF8584T/2,518 is available at Aetrix Electronics and suitable for industrial automation, legacy MCU upgrade projects, and embedded instrumentation requiring stable component supply over extended product lifecycles.
Supply support for PCF8584T/2,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep heritage in I²C technology originating from Philips.
The PCF8584T/2,518 belongs to NXP's legacy I²C interface controller product line, designed specifically to bridge parallel-bus microcontrollers to I²C-bus peripherals in cost-sensitive, high-reliability industrial systems.
FAQ
What is the primary function of the PCF8584T/2,518 in a system?
The PCF8584T/2,518 serves as a parallel-bus-to-I²C-bus protocol converter, enabling microcontrollers like the 8051, Z80, or 68000 to communicate with I²C peripherals without native I²C hardware. It handles all I²C timing, arbitration, START/STOP generation, and ACK/NACK signaling internally - offloading these tasks from the host CPU and ensuring protocol compliance. The PCF8584T/2,518 is essential for integrating I²C sensors, EEPROMs, or RTCs into legacy parallel-bus architectures.
How does the PCF8584T/2,518 detect whether it is connected to an 80XX or 68000-type microcontroller?
The PCF8584T/2,518 detects interface type automatically during initialization by monitoring the WR (R/W) and CS signal sequence: a HIGH-to-LOW transition on WR while CS is HIGH selects 68000 mode and enables DTACK output, whereas default behavior assumes 80XX mode. This detection occurs once at power-up or after reset and requires stable WR and CS signals post-reset. No firmware configuration is needed - the PCF8584T/2,518 adapts transparently to either bus timing convention.
Can the PCF8584T/2,518 operate as both I²C master and slave simultaneously?
No - the PCF8584T/2,518 operates in either master or slave mode per transaction, determined by firmware control of the STA (START) and STO (STOP) bits in register S1. It supports multi-master arbitration and can respond as a slave when addressed, but cannot maintain concurrent master and slave sessions. Mode selection is dynamic and software-controlled; for example, a single PCF8584T/2,518 may act as master to read sensor data and later as slave to accept configuration updates - but not at the same time.
What is required to enable the long-distance 4-wire mode on the PCF8584T/2,518?
To enable long-distance mode, set ES1 = 1 and ESO = 1 in register S1, and ensure ENI = 0 before entry. In this mode, pins 2–5 become unidirectional: SDA OUT, SCL IN, SDA IN, and SCL OUT - requiring external RS-422/485 line drivers. The PCF8584T/2,518 must be isolated from the 4-wire bus until fully initialized, and synchronization shifts from interrupt-driven (INT) to polled (PIN bit), since INT is disabled. Standard I²C timing and register access remain unchanged.
Does the PCF8584T/2,518 support I²C clock stretching, and how is it implemented?
Yes - the PCF8584T/2,518 supports clock stretching via automatic SCL hold-off. When acting as slave receiver and PIN = 0, it holds SCL LOW until the read buffer S0 is accessed; when acting as slave transmitter and PIN = 0, it holds SCL LOW until the next data byte is written to S0. This behavior is hardware-managed and requires no firmware intervention - ensuring compliant clock stretching that prevents data overrun and maintains I²C bus timing integrity during slow host processing.
PCF8584T/2,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Programmable:
- Not Verified
- Protocol:
- I2C
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Supply:
- 1.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 20-SO
- Grade:
- -
- Qualification:
- -
PCF8584T/2,518 FAQ
1.How can I place an order for PCF8584T/2,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for PCF8584T/2,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PCF8584T/2,518 reliable?
The price and inventory of PCF8584T/2,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PCF8584T/2,518 is usually 5 days.
3.What payment methods are accepted for PCF8584T/2,518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PCF8584T/2,518 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PCF8584T/2,518?
PCF8584T/2,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PCF8584T/2,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PCF8584T/2,518?
For technical support, including PCF8584T/2,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PCF8584T/2,518 requirements.
6.How does Aetrix verify that PCF8584T/2,518 is sourced from the original manufacturer or authorized distributors?
All PCF8584T/2,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PCF8584T/2,518 meets industry standards.
7.What is the process for return or replacement of PCF8584T/2,518?
All PCF8584T/2,518 units undergo pre-shipment inspection (PSI). If there is an issue with PCF8584T/2,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PCF8584T/2,518 part is unused and in its original packaging.
Return procedure for PCF8584T/2,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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