Texas Instruments PCM3500E/2K

Overview

PCM3500E/2K from Burr-Brown is a low-voltage, mono 16-bit voice/modem CODEC integrating delta-sigma ADC and DAC, on-chip crystal oscillator circuit, master/slave serial interface, and ADC-to-DAC loop-back mode - operating from +2.7V to +3.6V with 88dB dynamic range at 8kHz sampling and 60µA typical power-down current. It targets modem analog front ends supporting up to 56kbps operation in portable voice recorders and embedded speech systems.

For engineers reviewing the PCM3500E/2K datasheet, PCM3500E/2K pinout, PCM3500E/2K application, or PCM3500E/2K equivalent, key selection criteria include its SSOP-24 package, 7.2–26kHz programmable sampling rate, TDM time-slot support for up to four devices on one serial bus, and integrated analog filters enabling glue-free interfacing to DSPs and RISC processors.

Technical Context

The PCM3500E/2K implements dual delta-sigma modulators with decimation (ADC) and interpolation (DAC) digital filters, internal high-pass filter (HPF) with configurable disable control (HPFD), and anti-aliasing/output low-pass analog filtering. Its synchronous 4-wire serial interface supports DSP-format data transfer at 16fS (normal) or 64fS (TDM), with frame sync (FS) at fS and bit clock (BCK) synchronized to the 512fS system clock.

It operates in Master or Slave mode via M/S pin control, includes Schmitt-trigger inputs on critical control pins (M/S, TSC, HPFD, LOOP, PDWN), and features automatic synchronization loss detection that forces DAC output to VCOM and places DOUT in high-impedance state within one FS period if phase error exceeds ±1.5 BCK periods.

Key Specifications

Pinout & Package

PCM3500E/2K is housed in a 24-pin SSOP (Shrink Small Outline Package) with 0.635mm pitch, optimized for compact modem and voice peripheral designs. Thermal resistance ΘJA is 100°C/W, supporting operation from –25°C to +85°C ambient.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voice/modem CODEC applications.

Compared with TLV320AIC10IPFB and PCM3002E/2K, PCM3500E/2K uniquely combines on-chip crystal oscillator, TDM time-slot support, and ADC-to-DAC loop-back - making it the only option among the three enabling fully autonomous multi-CODEC modem subsystems without external timing or test infrastructure.

Availability

PCM3500E/2K is available at Aetrix Electronics and suitable for software modems, portable voice recorders, speech recognition terminals, and teleconferencing audio modules requiring stable component supply and long-term industrial availability.

Supply support for PCM3500E/2K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Burr-Brown Corporation was a U.S.-based analog semiconductor company specializing in precision data converters, amplifiers, and interface ICs before its acquisition by Texas Instruments in 2000.

The PCM3500 product line was designed specifically for low-power, low-cost voice and modem analog front ends - emphasizing integration of clock generation, filtering, and TDM-ready serial interfaces in a single SSOP package.

FAQ

What is the function of the HPFD pin on the PCM3500E/2K?

The HPFD (High-Pass Filter Disable) pin on the PCM3500E/2K is a Schmitt-trigger input with internal pull-down. When driven high (logic '1'), it disables the internal high-pass filter in the ADC path, allowing DC-coupled or sub-100Hz signal acquisition. This is essential for applications like vibration sensing or biomedical monitoring where baseband content must be preserved. The PCM3500E/2K default behavior (HPFD = low) applies DC blocking per ITU-T voice standards.

Does the PCM3500E/2K support simultaneous ADC and DAC operation?

Yes, the PCM3500E/2K supports full-duplex operation: the ADC continuously samples the VIN input while the DAC simultaneously reconstructs audio from DIN data, both synchronized to the same sampling frequency fS. This is confirmed by the datasheet's "ADC-to-DAC Loop-Back Mode" (enabled via LOOP pin) and timing diagrams showing concurrent DOUT and VOUT activity. The PCM3500E/2K achieves this with independent delta-sigma modulators and shared 512fS system clock domain.

What are the absolute maximum ratings for the PCM3500E/2K power supplies?

The PCM3500E/2K has separate analog (VCC) and digital (VDD) supply pins, each rated for +2.7V to +3.6V operating range. Absolute maximum ratings specify +6.5V for either supply, but exceeding +3.6V risks permanent damage. Supply voltage difference between VCC and VDD must not exceed ±0.1V, and ground potential differences must also stay within ±0.1V. These limits are defined in the Absolute Maximum Ratings table on page 3 of the PCM3500E/2K datasheet.

Can the PCM3500E/2K operate without an external crystal?

Yes, the PCM3500E/2K can operate without an external crystal by using an external master clock applied to either XTI (pin 17) or SCKIO (pin 15). When using SCKIO as clock input, XTI must be grounded. The required system clock frequency remains 512fS (3.686–13.312MHz), and the PCM3500E/2K's internal clock generation circuitry is bypassed. This configuration is explicitly supported in Figure 1 and Section 12 of the PCM3500E/2K datasheet.

How does the PCM3500E/2K handle loss of synchronization between FS and the system clock?

The PCM3500E/2K includes built-in synchronization monitoring: if phase error between FS and the 512fS system clock exceeds ±1.5 BCK periods, it detects loss of sync within one FS period. Upon detection, the DAC output is forced to VCOM (0.5VCC) and DOUT enters high-impedance state - preventing corrupted data propagation. Recovery occurs automatically once synchronization is restored, with defined delays (tADCDLY2, tDACDLY2) specified in Figure 10 of the PCM3500E/2K datasheet.