NXP Semiconductors PCU9669B,118

Overview

PCU9669B,118 from NXP Semiconductors is an advanced single-master I²C-bus controller with three independent channels: one Fast-mode Plus (Fm+) channel supporting 1 Mbit/s and two Ultra Fast-mode (UFm) channels each supporting 5 Mbit/s unidirectional data transfer. It features 4352-byte buffers per channel, parallel-bus interface (8-bit, 3.3 V), and integrated oscillator/PLL for autonomous sequence execution. It serves as a high-throughput protocol converter in LED matrix control and entertainment systems.

For engineers reviewing the PCU9669B,118 datasheet, PCU9669B,118 pinout, PCU9669B,118 application, or PCU9669B,118 equivalent, key selection considerations include Fm+/UFm channel topology differences, VDD(IO) voltage flexibility (3.0–5.5 V), JTAG boundary-scan support, trigger-synchronized frame looping, and 48-pin LQFP package compatibility with industrial PCB layouts.

Technical Context

The PCU9669B,118 implements a parallel-to-serial protocol conversion architecture with dedicated hardware sequencers per channel. Its internal 12 MHz oscillator and 156 MHz PLL generate precise timing for both I²C bus clocks and interval timers used in automatic frame retransmission.

Each channel operates independently with configurable slave address tables (up to 64 slaves), transaction-level error reporting (NACK detection on address/data), and maskable interrupts. The UFm channels use push-pull drivers eliminating external pull-ups, while the Fm+ channel retains open-drain SCL/SDA with 30 mA sink capability.

Key Specifications

Pinout & Package

Package: LQFP48 (7 × 7 × 1.4 mm, SOT313-2). All VDD pins (7, 18, 30, 40, 44, 48) must be externally tied together; all VSS pins (8, 19, 29, 35, 39, 43, 47) similarly connected. VDD(IO) (pin 24) sets I/O voltage reference; VSS(IO) (pin 23) is its dedicated ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C-bus controller applications.

Compared with PCA9665 and TCA9548A, the PCU9669B,118 uniquely delivers triple-channel autonomous I²C mastering with 5 Mbit/s UFm throughput, making it irreplaceable for applications demanding simultaneous high-speed and legacy bus control with minimal host intervention.

Availability

PCU9669B,118 is available at Aetrix Electronics and suitable for LED matrix control, entertainment systems, and data-intensive I²C-bus transfers requiring stable component supply, long-term industrial availability, and consistent parametric performance across temperature and voltage ranges.

Supply support for PCU9669B,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with leadership in interface, power management, and MCU technologies.

The PCU9669B,118 belongs to NXP's advanced I²C-bus controller product line, designed specifically to offload high-volume serial data transfers from host processors in bandwidth-constrained embedded systems.

FAQ

What is the maximum data rate supported by each I²C channel on the PCU9669B,118?

The PCU9669B,118 supports three distinct I²C channels: Channel 0 (Fm+) operates up to 1 Mbit/s with open-drain topology and supports clock stretching; Channels 1 and 2 (UFm) each support up to 5 Mbit/s unidirectional transfer using push-pull drivers - no external pull-ups required. This hybrid architecture allows concurrent legacy and high-speed peripheral interfacing within a single device.

Does the PCU9669B,118 require an external crystal or oscillator?

No, the PCU9669B,118 integrates a factory-trimmed 12 MHz oscillator (±1 % accuracy) and a 156 MHz PLL, eliminating the need for external timing components. These internal resources generate all required clocks for I²C bus operation, interval timers, and internal logic - reducing BOM count and board space while improving startup reliability.

How does the PCU9669B,118 handle I²C bus errors such as slave NACK conditions?

The PCU9669B,118 reports NACK errors at three levels: transaction (STATUSx_[n] registers), channel (CHSTATUS), and controller (CTRLSTATUS). For example, RSN (Read Slave NACK) or WDN (Write Data NACK) bits set in STATUSx_[n] trigger masked interrupts via the INT pin. Host software can then read specific status bytes to identify failed slaves and recover without resetting the entire channel.

Can the PCU9669B,118 communicate with more than one I²C slave per transaction sequence?

Yes, the PCU9669B,118 supports up to 64 unique slave addresses per channel via its SLATABLE register. A single preloaded sequence can interleave reads and writes across multiple slaves - for instance, writing configuration to 10 devices and reading status from 4 others - all executed autonomously after a single START command, with RESTART between slaves and STOP at sequence end.

What is the function of the TRIG pin on the PCU9669B,118?

The TRIG pin on the PCU9669B,118 provides hardware-synchronized initiation of stored sequence retransmission. When asserted, it starts the interval timer-controlled loop cycle - enabling precise alignment of I²C frame updates with external events like video vertical blanking, audio sample clocks, or PLC scan cycles - critical for deterministic real-time system behavior.