STMicroelectronics PD57018S
- Part No.:
- PD57018S
- Manufacturer:
- STMicroelectronics
- Category:
- Single FETs, MOSFETs
- Package:
- PowerSO-10 Exposed Bottom Pad
- Datasheet:
-
PD57018S.pdf
- Description:
- RF MOSFET LDMOS 28V POWERSO10
- Quantity:
- Payment:

- Shipping:

Inventory:9,673
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PD57018S from STMicroelectronics is an N-channel enhancement-mode lateral MOSFET RF power transistor in common-source configuration, designed for 925–960 MHz base station amplifiers. It delivers 18 W output power at 945 MHz with 16.5 dB power gain and 53% drain efficiency under 28 V supply and 100 mA quiescent current, housed in the JEDEC-approved PowerSO-10RF straight-lead plastic package.
For engineers reviewing the PD57018S datasheet, PD57018S pinout, PD57018S application, or PD57018S equivalent, key selection criteria include its 65 V drain-source breakdown voltage, 3.0 °C/W junction-to-case thermal resistance, 34.5 pF input capacitance, gate-source voltage range of ±20 V, and verified S-parameter performance up to 1.5 GHz under multiple bias conditions.
Technical Context
This device implements ST's LDMOS technology optimized for broadband RF power amplification in cellular infrastructure. Its lateral structure provides excellent thermal stability and linearity-critical for multi-carrier GSM/UMTS base station transmitters operating under high VSWR (10:1) conditions.
The PowerSO-10RF straight-lead package enables surface-mount assembly while maintaining low-inductance source grounding and efficient heat transfer via exposed drain pad. Impedance data (e.g., ZIN = 0.53 − j0.86 Ω at 945 MHz) supports matching network design for narrowband and broadband PA stages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V(BR)DSS | 65 V - Withstands transient overvoltage events in 28 V DC-fed RF amplifier stages without breakdown. |
| POUT @ 945 MHz | 18 W - Delivers sufficient output for macrocell or microcell BTS final-stage amplification. |
| GPS | 16.5 dB typ - Enables high-gain two-stage PA designs with minimal driver stage complexity. |
| ηD | 53 % typ - Reduces thermal load and power supply requirements in continuous-wave operation. |
| Rth(j-c) | 3.0 °C/W - Supports reliable operation at TCASE ≤ 70 °C with standard heatsinking. |
| CISS | 34.5 pF @ 1 MHz - Defines input matching network component values and bandwidth constraints. |
| VGS(Q) | 2.0–5.0 V - Specifies gate bias window for stable Class AB operation at 100 mA IDQ. |
Pinout & Package
PD57018S uses the PowerSO-10RF straight-lead plastic package (JEDEC MO-235), featuring an exposed drain pad for thermal conduction and three main terminals: Gate (G), Source (S), and Drain (D). The package measures 9.5 mm × 15.4 mm × 1.67 mm (L × E × A2) with gull-wing–compatible lead geometry optimized for RF layout integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GATE | Control electrode | Receives DC bias and RF input signal; requires stable 2–5 V gate drive and low-impedance AC path to ground. |
| SOURCE | Common reference node | Internally tied to exposed metal slug; must be low-inductance RF ground connection for stability. |
| DRAIN | Power output node | High-current RF output terminal; connected to external matching network and heatsink via exposed pad. |
Key Features
| Feature | Design Value |
|---|---|
| Common-source configuration | Enables standard RF PA topology with single-ended input/output and inherent isolation between ports. |
| PowerSO-10RF straight-lead package | JEDEC-qualified SMD footprint enabling automated assembly while maintaining RF performance and thermal reliability. |
| 10:1 load mismatch tolerance | Stable operation under severe antenna VSWR conditions typical in outdoor base station deployments. |
| Lateral LDMOS process | Delivers superior linearity (low IM3) and ruggedness versus vertical MOSFETs at UHF frequencies. |
| 3.0 °C/W Rth(j-c) | Allows ≥31.7 W power dissipation at 70 °C case temperature-critical for uncooled or passively cooled modules. |
Applications
| Cellular Base Station Transmitter | GSM/UMTS Macrocell PA |
|---|---|
Use Scenario: Final-stage RF power amplification in 900 MHz band cellular base stations handling multiple carriers and high peak-to-average power ratios. IC Role / Device Role / Timing Role: High-efficiency, high-linearity N-channel RF power transistor operating in Class AB mode at 28 V supply. Use Value: Delivers 18 W POUT with 16.5 dB gain and 53% efficiency-reducing system-level power conversion losses and thermal management burden. | Use Scenario: Driver or final-stage amplifier in macrocell BTS cabinets requiring ruggedness against antenna mismatch and long-term reliability. IC Role / Device Role / Timing Role: Common-source lateral MOSFET providing broadband gain and stable operation across 925–960 MHz. Use Value: 10:1 VSWR tolerance ensures uninterrupted transmission during antenna detuning or environmental degradation. |
| Industrial RF Heating Amplifier | Land Mobile Radio (LMR) Repeater |
Use Scenario: Solid-state RF generator for industrial heating systems operating near 945 MHz with continuous duty cycle. IC Role / Device Role / Timing Role: Primary power switching element delivering high CW output into tuned resonant loads. Use Value: 165 °C max junction temperature and 3.0 °C/W thermal resistance support sustained 18 W operation without active cooling. | Use Scenario: Output stage in wide-area LMR repeaters deployed in public safety networks covering rural terrain. IC Role / Device Role / Timing Role: High-reliability RF power transistor in linear amplifier modules supporting analog FM and digital P25 waveforms. Use Value: Excellent gain flatness (±0.5 dB over 925–960 MHz) and low intermodulation distortion ensure clean signal retransmission. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MRF6V2150N | Higher POUT (150 W), GaN-on-SiC, 28 V, but requires more complex gate biasing and thermal management. | Targeted at high-power macrocell and massive MIMO systems-not drop-in compatible due to different package and bias scheme. | Select when >50 W output or >2.5 GHz operation is required; avoid for cost-sensitive 900 MHz legacy upgrades. |
| PD57003S | Same PowerSO-10RF package, lower POUT (3 W), 16.5 dB gain at 945 MHz, reduced V(BR)DSS (40 V). | Designed for driver-stage amplification only; insufficient for final-stage use in macrocell BTS. | Use as pre-driver for PD57018S in two-stage architectures; not suitable as direct replacement in final PA position. |
Compared with MRF6V2150N and PD57003S, PD57018S uniquely balances 18 W output, proven LDMOS ruggedness, JEDEC-standard SMD packaging, and straightforward 28 V/Class AB biasing-making it optimal for mid-power 900 MHz infrastructure where reliability, manufacturability, and thermal simplicity are prioritized.
Availability
PD57018S is available at Aetrix Electronics and suitable for cellular base station transmitters, industrial RF heating systems, land mobile radio repeaters, and broadband wireless infrastructure requiring stable component supply and long-lifecycle support.
Supply support for PD57018S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in analog, power, and RF technologies for industrial, automotive, and communications markets.
PD57018S belongs to ST's LdmoST Plastic family of RF power transistors, engineered specifically for high-efficiency, high-linearity amplification in 400 MHz–2.5 GHz cellular infrastructure equipment.
FAQ
What is the maximum safe operating drain voltage for PD57018S?
The absolute maximum drain-source voltage (V(BR)DSS) is 65 V at TCASE = 25 °C with VGS = 0 V and IDS = 10 mA. Operation above 28 V DC supply is permissible only during transient conditions within SOA limits; sustained operation must remain within 28 V for rated POUT and thermal safety.
Does PD57018S require external gate protection diodes?
No-PD57018S integrates internal gate protection and is rated for ±20 V gate-source voltage. However, external RC snubbers (e.g., 10 Ω + 100 pF) are recommended at the gate input to suppress RF-induced ringing and improve stability in broadband matching networks.
How does PD57018S differ from PD57018 (formed-lead version)?
PD57018S uses straight leads for standard SMT placement, while PD57018 uses formed (gull-wing) leads. Both share identical die, electrical specs, and thermal performance. Mechanical dimensions differ slightly-E dimension is 15.4 mm (PD57018S) vs. 14.1 mm (PD57018)-requiring separate PCB footprints.
Can PD57018S operate reliably at 1.2 A quiescent current?
Yes-S-parameter data confirms stable small-signal gain (S21) and return loss (S11) at IDQ = 1.2 A and VDS = 28 V across 50–1500 MHz. However, thermal derating is required: at 1.2 A, PDISS rises significantly, limiting usable POUT unless case temperature is maintained below 55 °C.
PD57018S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- PowerSO-10 Exposed Bottom Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Technology:
- LDMOS
- Configuration:
- -
- Frequency:
- 945MHz
- Gain:
- 16.5dB
- Voltage - Test:
- 28 V
- Current Rating (Amps):
- 2.5A
- Noise Figure:
- -
- Current - Test:
- 100 mA
- Power - Output:
- 18W
- Voltage - Rated:
- 65 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- 10-PowerSO
PD57018S FAQ
1.How can I place an order for PD57018S through Aetrix?
Please submit a Request for Quotation (RFQ) for PD57018S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PD57018S reliable?
The price and inventory of PD57018S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PD57018S is usually 5 days.
3.What payment methods are accepted for PD57018S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PD57018S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PD57018S?
PD57018S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PD57018S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PD57018S?
For technical support, including PD57018S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PD57018S requirements.
6.How does Aetrix verify that PD57018S is sourced from the original manufacturer or authorized distributors?
All PD57018S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PD57018S meets industry standards.
7.What is the process for return or replacement of PD57018S?
All PD57018S units undergo pre-shipment inspection (PSI). If there is an issue with PD57018S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PD57018S part is unused and in its original packaging.
Return procedure for PD57018S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PD57018S Tags

-
3SK294(TE85L,F)
Toshiba Semiconductor and Storage
-
SAV-551+
Mini-Circuits

-
TAV2-501+
Mini-Circuits

-
CE3514M4-C2
CEL

-
AFT05MS004NT1
NXP USA Inc.
-
SAV-541+
Mini-Circuits

-
CE3512K2-C1
CEL

-
AFM907NT1
NXP Semiconductors

-
SKY65050-372LF
Skyworks Solutions Inc.

-
CE3520K3-C1
CEL

-
AFT09MS007NT1
NXP USA Inc.

-
AFT09MS015NT1
NXP USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

.jpg)