STMicroelectronics PD85035S-E

Overview

PD85035S-E from STMicroelectronics is an N-channel enhancement-mode lateral MOSFET RF power transistor in PowerSO-10RF straight-lead package, operating at 13.6 V with 35 W P_OUT, 14.9 dB gain, and 60–72% drain efficiency at 870 MHz in common-source configuration for mobile radio amplification.

For engineers reviewing the PD85035S-E datasheet, PD85035S-E pinout, PD85035S-E application, or PD85035S-E equivalent, this device is selected for high-linearity, broadband RF power stages requiring stable thermal performance, ESD protection, and JEDEC-qualified SMD mounting in automotive and industrial transmitters.

Technical Context

This LDMOS transistor uses lateral structure for improved thermal stability and linearity up to 1 GHz. Its common-source topology supports broadband matching with Z_IN = 0.57 + j0.73 Ω and Z_DL = 1.73 – j0.15 Ω at 870 MHz, enabling robust load mismatch tolerance (20:1 VSWR).

Static parameters include V_GS(Q) = 3.4–4.6 V at I_D = 250 mA and low on-resistance (V_DS(ON) = 0.64–0.7 V @ I_D = 3 A), while dynamic operation delivers 35–40 W P_3dB with 15–17 dB power gain under 13.6 V bias and 350 mA quiescent current.

Key Specifications

Pinout & Package

PD85035S-E uses the PowerSO-10RF straight-lead plastic package - ST's first JEDEC-approved high-power SMD RF package, optimized for thermal dissipation and RF performance with formed lead alternatives available.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar RF power amplifier applications.

Compared with PD85035-E and MRF6P21140HR5, PD85035S-E offers identical RF performance in a straight-lead SMD package-enabling simplified pick-and-place assembly and compatibility with standard reflow profiles-while maintaining full thermal and linearity capability for mobile radio use cases.

Availability

PD85035S-E is available at Aetrix Electronics and suitable for car mobile radio transmitters, industrial UHF repeaters, and commercial base station amplifiers requiring stable component supply, JEDEC-qualified SMD packaging, and long-term lifecycle support.

Supply support for PD85035S-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, power, microcontroller, and RF components for industrial, automotive, and consumer markets.

PD85035S-E belongs to ST's LdmoST plastic family of RF power transistors-engineered specifically for high-gain, broadband commercial and industrial transmitters operating up to 1 GHz with emphasis on thermal stability and SMD manufacturability.

FAQ

What is the maximum operating frequency of PD85035S-E?

The PD85035S-E is characterized for operation up to 1 GHz, with full performance data specified at 870 MHz including 35 W P_OUT, 14.9 dB gain, and 60–72% drain efficiency. Its lateral LDMOS structure maintains stable gain and linearity across this band, and impedance data confirms usable matching up to 1 GHz.

How does the PowerSO-10RF package improve thermal performance?

The PowerSO-10RF package features an exposed thermal pad directly bonded to the MOSFET die, achieving a junction-to-case thermal resistance of 1.0 °C/W. This allows efficient heat transfer to the PCB ground plane or external heatsink without mechanical fasteners, enabling compact, fanless designs in mobile and industrial RF amplifiers.

Is PD85035S-E suitable for pulsed RF operation?

Yes - the device supports pulsed operation within its absolute maximum ratings: peak drain current ≤ 8 A, peak drain-source voltage ≤ 40 V, and pulse duty cycle limited by average power dissipation (95 W @ T_CASE = 70 °C). Thermal design must account for RMS power and transient junction temperature rise per pulse envelope.

What bias conditions are required for optimal linearity at 870 MHz?

For optimal linearity at 870 MHz, ST specifies V_DD = 13.6 V, I_DQ = 350 mA, and gate bias set to achieve V_GS(Q) = 3.4–4.6 V. This quiescent point balances gain flatness, intermodulation distortion, and efficiency, as validated in Figures 9–10 of the datasheet showing gain and efficiency vs. P_OUT.