STMicroelectronics PD85050S
- Part No.:
- PD85050S
- Manufacturer:
- STMicroelectronics
- Category:
- Single FETs, MOSFETs
- Package:
- PowerSO-10RF Exposed Bottom Pad (2 Straight Leads)
- Datasheet:
-
PD85050S.pdf
- Description:
- RF MOSFET LDMOS 13.6V PWRSO-10RF
- Quantity:
- Payment:

- Shipping:

Inventory:3,331
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Product details
Overview
PD85050S from STMicroelectronics is a common-source N-channel enhancement-mode lateral MOSFET RF power transistor designed for broadband commercial and industrial amplifiers. It delivers >50 W output power with 12 dB gain at 870 MHz under 13.6 V supply, features unmatched wideband operation from 1–1000 MHz, bi-directional ESD protection, and is housed in the PowerSO-10RF plastic SMD package.
For engineers reviewing the PD85050S datasheet, PD85050S pinout, PD85050S application, or PD85050S equivalent, this device is selected for high-linearity mobile radio transmitters requiring stable gain, thermal robustness, and 50 W saturated RF output in compact surface-mount form.
Technical Context
The PD85050S operates in common-source configuration with gate-controlled enhancement-mode conduction, optimized for linear Class AB RF amplification up to 1 GHz. Its LDMOS structure enables high transconductance (8 S typical), low output capacitance (COSS = 70 pF), and excellent thermal resistance (RthJC = 0.9 °C/W).
It supports wideband impedance matching across 100–960 MHz via tunable input (ZIN) and drain-load (ZDL) impedances, and maintains stable performance under load mismatch up to 65:1 VSWR - critical for mobile radio front-end resilience.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Frequency | 1 MHz to 1000 MHz - supports full UHF band including TETRA (380–400 MHz), DMR (440–470 MHz), and cellular 870 MHz bands. |
| Output Power (POUT) | 50–55 W @ 870 MHz, 13.6 V - sufficient for high-power mobile radio final stages without external combiners. |
| Power Gain (GP) | 10–12 dB @ POUT = 50 W - enables single-stage amplification from driver-level input (e.g., 4 W) to 50 W output. |
| Drain-Source Voltage (V(BR)DSS) | 50 V - allows safe operation with 13.6 V nominal supply plus transient headroom in automotive environments. |
| Junction-to-Case Thermal Resistance | 0.9 °C/W - enables high-power dissipation (105 W max) with moderate heatsinking in compact PowerSO-10RF footprint. |
| ESD Protection Level | HBM Class 2, MM Class M3 - provides robust handling during PCB assembly and field operation without external protection diodes. |
| Drain Efficiency (hD) | 55–60% @ POUT = 50 W - balances RF output power and thermal load for sustained duty-cycle operation. |
Pinout & Package
PD85050S is housed in the PowerSO-10RF plastic surface-mount package (straight lead), ST's first JEDEC-approved high-power SMD RF package. Its thermally enhanced design integrates a large exposed drain pad for direct heatsink attachment and optimized RF grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Gate | Control electrode | Enhancement-mode N-channel gate requiring ≥2 V threshold; biased at ~5–7 V for linear Class AB operation. |
| Source | Common reference node | Internally connected to exposed metal pad; serves as RF ground return and thermal path to PCB heatsink. |
| Drain | High-power RF output terminal | Connected to large exposed copper area on bottom of package; carries full RF output current and DC bias. |
Key Features
| Feature | Design Value |
|---|---|
| Unmatched wideband operation | Eliminates need for external matching networks across 1–1000 MHz, reducing BOM count and layout complexity. |
| Bi-directional ESD protection | Integrated protection on gate and drain terminals enables direct interface with antenna switches and filters without discrete TVS. |
| High linearity for digital modulations | Meets ACLR and EVM requirements for TETRA, DMR, and SSB waveforms without predistortion circuitry. |
| Thermal stability at 165 °C TJ | Enables reliable operation in sealed vehicle enclosures where ambient temperatures exceed 85 °C. |
| PowerSO-10RF mechanical compliance | JEDEC-standardized footprint ensures compatibility with automated SMT placement and reflow profiles for high-volume production. |
Applications
| Land Mobile Radio Transceivers | Public Safety Base Stations |
|---|---|
|
Use Scenario: Final RF power amplifier in 380–470 MHz TETRA/DMR handheld and mobile radios. IC Role / Device Role / Timing Role: High-efficiency, high-linearity Class AB RF power stage delivering 50 W POUT into 50 Ω load. Use Value: Enables single-transistor 50 W output with <60% drain efficiency and <−35 dBc ACLR, meeting ETSI EN 300 392-2 spectral mask. |
Use Scenario: Linear repeater amplifier in 800–960 MHz public safety trunked systems. IC Role / Device Role / Timing Role: Driver or final stage in multi-carrier base station PA modules supporting simultaneous voice and data channels. Use Value: Maintains gain flatness ±0.5 dB and load mismatch tolerance up to 65:1 VSWR, ensuring stable operation with dynamic antenna coupling. |
| Amateur Radio HF/UHF Amplifiers | Industrial Wireless Link Transmitters |
|
Use Scenario: Homebrew or OEM HF (1.8–30 MHz) and UHF (430–440 MHz) linear amplifiers for contesting and emergency comms. IC Role / Device Role / Timing Role: Single-ended broadband power device operating from 1 MHz to 1 GHz without band-switching. Use Value: Simplifies design by eliminating mechanical bandswitches and external matching components while retaining >10 dB gain across bands. |
Use Scenario: High-reliability transmitter in oilfield telemetry, SCADA, and remote monitoring systems. IC Role / Device Role / Timing Role: Robust RF output stage operating continuously at elevated ambient temperatures (−40 °C to +85 °C). Use Value: Delivers 50 W output with RthJC = 0.9 °C/W and 165 °C max junction temperature, enabling passive heatsinking in sealed outdoor enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MRF6VP11KHR5 | Higher V(BR)DSS (110 V), higher POUT (125 W), requires external gate bias network; larger TO-272 package. | Better suited for 28 V base station applications; not drop-in compatible due to voltage rating and footprint. | Select when >100 W output or 28 V supply is required; avoid for 13.6 V mobile designs due to over-spec and cost penalty. |
| PD57003-E | Lower POUT (30 W), same PowerSO-10RF package, 50 V V(BR)DSS, optimized for 700–2700 MHz LTE bands. | Targeted at higher-frequency infrastructure; insufficient output power for 50 W mobile radio use cases. | Choose only for sub-30 W UHF/LTE applications where footprint compatibility is critical but power demand is lower. |
Compared with MRF6VP11KHR5 and PD57003-E, the PD85050S uniquely balances 50 W output, 13.6 V compatibility, wideband 1–1000 MHz operation, and PowerSO-10RF manufacturability - making it the optimal choice for cost-sensitive, high-volume land mobile radio amplifiers.
Availability
PD85050S is available at Aetrix Electronics and suitable for land mobile radio transceivers, public safety base stations, amateur radio amplifiers, and industrial wireless link transmitters requiring stable component supply, consistent RF performance, and long-term lifecycle support.
Supply support for PD85050S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in analog, power, microcontrollers, and RF solutions for industrial, automotive, and communications markets.
The PD85050S belongs to ST's LdmoST family of RF power transistors, engineered specifically for high-linearity, wideband mobile radio amplification - emphasizing thermal reliability, ESD robustness, and SMD manufacturability in harsh environments.
FAQ
What is the recommended gate bias voltage for linear operation?
The PD85050S achieves optimal linearity and efficiency at IDQ = 500 mA with VGS ≈ 5.5–6.5 V, verified in the datasheet's Figure 5–7 loadline curves. A stable, low-noise gate bias network using a 10 kΩ potentiometer and 100 nF bypass capacitor is advised to maintain quiescent current within ±5% across temperature.
Can PD85050S be used in push-pull configuration?
Yes - its matched static parameters (VP = 2–4 V, GFS = 8 S typ) and symmetrical thermal profile support balanced push-pull operation. However, external gate drive isolation and individual source degeneration resistors are required to ensure current sharing; no internal circuitry enables direct paralleling.
Is the PowerSO-10RF package RoHS-compliant and lead-free?
Yes - the PD85050S is manufactured in ST's ECOPACK®-compliant PowerSO-10RF package, meeting RoHS Directive 2011/65/EU and JEDEC J-STD-020B MSL 3 moisture sensitivity level. Lead-free reflow profile peak temperature is 260 °C, with ramp rates per JEDEC standards.
Does PD85050S require external input/output matching networks?
No - it is an unmatched device optimized for direct 50 Ω system integration. Input and output impedance data (Tables 8–10) confirm ZIN and ZDL are designed for minimal external tuning; only a simple gate DC blocking capacitor and drain RF choke are needed for basic biasing.
PD85050S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- PowerSO-10RF Exposed Bottom Pad (2 Straight Leads)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- LDMOS
- Configuration:
- -
- Frequency:
- 870MHz
- Gain:
- 12dB
- Voltage - Test:
- 13.6 V
- Current Rating (Amps):
- 1µA
- Noise Figure:
- -
- Current - Test:
- 500 mA
- Power - Output:
- 55W
- Voltage - Rated:
- 50 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- PowerSO-10RF (Straight Lead)
PD85050S FAQ
1.How can I place an order for PD85050S through Aetrix?
Please submit a Request for Quotation (RFQ) for PD85050S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PD85050S reliable?
The price and inventory of PD85050S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PD85050S is usually 5 days.
3.What payment methods are accepted for PD85050S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PD85050S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PD85050S?
PD85050S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PD85050S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PD85050S?
For technical support, including PD85050S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PD85050S requirements.
6.How does Aetrix verify that PD85050S is sourced from the original manufacturer or authorized distributors?
All PD85050S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PD85050S meets industry standards.
7.What is the process for return or replacement of PD85050S?
All PD85050S units undergo pre-shipment inspection (PSI). If there is an issue with PD85050S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PD85050S part is unused and in its original packaging.
Return procedure for PD85050S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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