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Nexperia USA Inc. PDTA113ET,215
- Part No.:
- PDTA113ET,215
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PDTA113ET,215.pdf
- Description:
- TRANS PREBIAS PNP 50V TO236AB
- Quantity:
- Payment:
- Shipping:
Inventory:2,900
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Product details
Overview
PDTA113ET from Nexperia is a PNP resistor-equipped transistor (RET) designed for general-purpose switching in low-voltage digital interface circuits, featuring integrated bias resistors R1 = 1 kΩ and R2 = 1 kΩ, −50 V VCEO rating, −100 mA DC output current, and SOT23 surface-mount package. It simplifies BJT-based level translation and logic inversion in space-constrained consumer and industrial control modules.
For engineers reviewing the PDTA113ET datasheet, PDTA113ET pinout, PDTA113ET application, or PDTA113ET equivalent, this page delivers verified pin configuration, real-world switching use cases, thermal derating guidance, and validated alternative parts with documented functional trade-offs for discrete logic interface design.
Technical Context
This device integrates two precision silicon resistors (R1 = 1 kΩ, R2/R1 = 1 ± 0.2) directly into a PNP bipolar transistor die to eliminate external base bias components. Its internal resistor network enables direct connection to 3.3 V or 5 V CMOS/TTL logic outputs without external pull-up or current-limiting resistors.
The SOT23 package supports reflow soldering only, with a 250 mW power dissipation limit at 25 °C ambient and 500 K/W junction-to-ambient thermal resistance. Device operation is specified across −40 °C to +150 °C junction temperature, with guaranteed VI(on) ≤ −1.7 V at IC = −20 mA and VI(off) ≥ −1.3 V at IC = −100 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −50 V - Maximum safe collector-emitter voltage under open-base conditions; supports 24 V rail switching with margin. |
| IO (DC) | −100 mA - Continuous collector current capability; sufficient for driving LEDs, small relays, or logic gate inputs. |
| R1 | 1 kΩ ±30% - Integrated input bias resistor; sets base current for predictable turn-on without external component. |
| R2/R1 | 1 ±0.2 - Matched feedback resistor ratio; ensures stable saturation and prevents latch-up in digital switching. |
| VCEsat | −150 mV max at IC = −30 mA, IB = −1.5 mA - Low saturation voltage reduces power loss and heat generation in on-state. |
| hFE | 30 min at VCE = −5 V, IC = −40 mA - Minimum DC current gain; guarantees reliable switching with defined drive margins. |
| Cc | 2 pF max at VCB = −10 V, f = 1 MHz - Low collector capacitance minimizes signal delay in high-speed digital interfaces. |
Pinout & Package
SOT23 (TO-236AB) plastic surface-mounted package; 3 leads, 1.1 mm × 1.0 mm × 0.95 mm body, gull-wing terminations, reflow-only assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | input (base) | Connected internally to R1 and R2; accepts logic-level input directly from MCU GPIO or buffer output. |
| 2 | GND (emitter) | Common reference terminal; tied to system ground; forms return path for base and collector currents. |
| 3 | output (collector) | Switched output node; sinks current when active; connects to load (e.g., LED cathode, relay coil, or next-stage input). |
Key Features
| Feature | Design Value |
|---|---|
| Integrated R1 + R2 bias network | Eliminates two external resistors per switch, reducing BOM count and PCB area in multi-channel interface designs. |
| Guaranteed R2/R1 matching | Ratio tolerance of ±20% ensures consistent saturation behavior across production lots and temperature ranges. |
| Low VI(on) threshold | Turns on fully with −1.7 V input, compatible with 3.3 V LVTTL and 5 V CMOS logic families without level shifters. |
| −150 mV VCEsat | Minimizes conduction loss in high-duty-cycle applications such as PWM-driven indicators or sensor interface enable lines. |
| JEDEC TO-236AB footprint | Enables drop-in replacement with standard SOT23 discrete transistors and compatibility with existing pick-and-place tooling. |
Applications
| LED Driver Circuit | Microcontroller GPIO Expander |
|---|---|
Use Scenario: Driving multiple status LEDs from a 3.3 V microcontroller with limited GPIO current capability. IC Role / Device Role / Timing Role: PNP switch sinking LED current through collector to ground-referenced anodes; operates in saturated switching mode. Use Value: Eliminates need for external base resistors and reduces layout complexity while maintaining <150 mV dropout across all operating temperatures. |
Use Scenario: Adding buffered digital outputs to an MCU with no hardware I²C/SPI port expansion available. IC Role / Device Role / Timing Role: Level-shifting and current-boosting stage between MCU GPIO and higher-current peripheral enable lines. Use Value: Provides −100 mA sink capability per channel with guaranteed −1.7 V VI(on), enabling reliable activation of sensors, displays, or power rails. |
| Logic Inverter Stage | Power Supply Enable Control |
Use Scenario: Converting active-high control signals to active-low enable inputs for legacy peripherals. IC Role / Device Role / Timing Role: Single-transistor inverter with built-in bias; provides clean logic inversion with <10 ns propagation delay. Use Value: Achieves rail-to-rail inversion without external components, reducing signal path skew and improving timing margin in mixed-voltage systems. |
Use Scenario: Enabling/disabling a 12 V auxiliary power rail using a 3.3 V system controller. IC Role / Device Role / Timing Role: High-side switch driver (with external P-MOSFET) or direct low-side enable switch for LDO/DC-DC EN pins. Use Value: Supports −50 V VCEO rating and −100 mA IO, allowing safe interfacing with 12 V domains while maintaining logic-level compatibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC113ET | NPN complement with identical R1/R2 values and SOT23 package; requires inverted logic drive. | Used where active-high input control is preferred or where NPN topology matches existing schematic conventions. | Select when sourcing current from VCC is required instead of sinking to GND; verify logic polarity alignment in firmware. |
| EMH11T2R | PNP RET with R1 = 2.2 kΩ, R2 = 47 kΩ; higher input impedance but lower gain and slower switching. | Better suited for high-impedance microcontroller inputs or battery-powered wake-up detection circuits. | Choose for ultra-low standby current (<1 µA) applications where VI(off) > −0.5 V is critical; not recommended for 20+ mA loads. |
Compared with PDTC113ET, PDTA113ET provides native active-low switching with ground-referenced output, while EMH11T2R trades off speed and current drive for significantly lower input leakage-making each suitable for distinct interface architecture requirements.
Availability
PDTA113ET is available at Aetrix Electronics and suitable for LED driver circuits, microcontroller GPIO expansion, logic inverter stages, and power supply enable control requiring stable component supply and full traceability.
Supply support for PDTA113ET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor leader specializing in high-volume discrete, logic, and PowerMOS devices, with core expertise in automotive, industrial, and consumer electronics.
The PDTA113ET belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered to reduce component count and improve reliability in digital interface and switching applications across cost-sensitive and space-constrained designs.
FAQ
What is the maximum continuous collector current for PDTA113ET?
The maximum continuous DC collector current (IO) is −100 mA, tested under standard mounting conditions with Tamb ≤ 25 °C. Derating is required above 25 °C ambient per the 500 K/W thermal resistance specification; at 70 °C ambient, usable current drops to approximately −65 mA to maintain Tj ≤ 150 °C.
Can PDTA113ET be used with 1.8 V logic inputs?
No-PDTA113ET requires a minimum VI(on) of −1.7 V to ensure full saturation, making it incompatible with 1.8 V logic families. It is optimized for 3.3 V and 5 V CMOS/TTL systems where input high levels exceed −2 V. For 1.8 V interfaces, consider a logic-level MOSFET or a dedicated level translator.
Is reflow soldering mandatory for PDTA113ET?
Yes-Nexperia specifies reflow soldering as the only recommended method for SOT23-packaged PDTA113ET. Wave soldering and hand soldering are not qualified due to thermal stress risks on the internal resistor network and bond wires. Peak reflow temperature must not exceed 260 °C for ≤10 seconds per JEDEC J-STD-020.
How does the R2/R1 ratio affect switching performance?
A nominal R2/R1 ratio of 1 ensures the base-emitter junction remains forward-biased during saturation while preventing excessive base current that could degrade hFE or cause thermal instability. Deviations beyond ±0.2 increase risk of incomplete turn-off or reduced current gain, particularly at elevated temperatures or high-frequency switching (>100 kHz).
PDTA113ET,215 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Transistor Type:
- PNP - Pre-Biased
- Current - Collector (Ic) (Max):
- 100 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 1 kOhms
- Resistor - Emitter Base (R2):
- 1 kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 30 @ 40mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 1.5mA, 30mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 250 mW
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TO-236AB
PDTA113ET,215 FAQ
1.How can I place an order for PDTA113ET,215 through Aetrix?
Please submit a Request for Quotation (RFQ) for PDTA113ET,215 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PDTA113ET,215 reliable?
The price and inventory of PDTA113ET,215 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PDTA113ET,215 is usually 5 days.
3.What payment methods are accepted for PDTA113ET,215?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PDTA113ET,215 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PDTA113ET,215?
PDTA113ET,215 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PDTA113ET,215 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PDTA113ET,215?
For technical support, including PDTA113ET,215 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PDTA113ET,215 requirements.
6.How does Aetrix verify that PDTA113ET,215 is sourced from the original manufacturer or authorized distributors?
All PDTA113ET,215 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTA113ET,215 meets industry standards.
7.What is the process for return or replacement of PDTA113ET,215?
All PDTA113ET,215 units undergo pre-shipment inspection (PSI). If there is an issue with PDTA113ET,215, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTA113ET,215 part is unused and in its original packaging.
Return procedure for PDTA113ET,215:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PDTA113ET,215 Tags
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MUN5211T1G
onsemi
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DTC043ZEBTL
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DTC114EKAT146
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DDTD113ZC-7-F
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DRDNB16W-7
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PDTC114ET,215
Nexperia USA Inc.
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MMUN2211LT1G
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