NXP Semiconductors PDTA114TEF,115
- Part No.:
- PDTA114TEF,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- SC-89, SOT-490
- Datasheet:
-
PDTA114TEF,115.pdf
- Description:
- TRANS PREBIAS PNP 50V 0.1A SC89
- Quantity:
- Payment:

- Shipping:

Inventory:3,090
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Product details
Overview
PDTA114TEF,115 from Nexperia is a PNP resistor-equipped transistor (RET) in SOT416 (SC-75) package, designed for digital switching applications with integrated 10 kΩ input bias resistor (R1), −50 V VCEO, −100 mA IO, and −150 mV VCEsat at IC = −10 mA/IB = −0.5 mA. It replaces discrete base-resistor + transistor combinations in low-power logic interface circuits.
For engineers reviewing the PDTA114TEF,115 datasheet, PDTA114TEF,115 pinout, PDTA114TEF,115 application, or PDTA114TEF,115 equivalent, key selection criteria include its single-input RET topology, SOT416 thermal resistance (833 K/W), guaranteed hFE ≥200 at −1 mA collector current, and suitability for space-constrained digital control nodes.
Technical Context
This PNP RET integrates a precision 10 kΩ input resistor (R1) with no internal R2 connection (R2 = open), enabling direct TTL/CMOS-level drive without external bias components. Its simplified three-terminal structure eliminates base resistor layout and reduces BOM count.
It operates as a saturated switch with guaranteed VCEsat ≤ −150 mV under −10 mA load and −0.5 mA base drive, supporting reliable logic-level translation in battery-powered and low-voltage embedded systems where power efficiency and board area are critical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −50 V - Maximum safe collector-emitter voltage with base open; defines off-state blocking capability in digital switches. |
| IO | −100 mA - Continuous output current rating; supports driving LEDs, small relays, or logic inputs without derating at Tamb ≤25 °C. |
| R1 | 7–13 kΩ (typ. 10 kΩ) - Integrated input bias resistor tolerance; enables direct microcontroller GPIO connection without external pull-up/down. |
| VCEsat | ≤ −150 mV at IC = −10 mA / IB = −0.5 mA - Low saturation voltage ensures minimal power loss and high noise margin in logic interfaces. |
| hFE | ≥200 at VCE = −5 V, IC = −1 mA - Minimum DC current gain guarantees robust turn-on even with weak drive signals. |
| Ptot | 150 mW at Tamb ≤25 °C - Power dissipation limit in free-air; requires thermal consideration in dense PCB layouts. |
| Rth(j-a) | 833 K/W - Junction-to-ambient thermal resistance in FR4 PCB; informs temperature rise under continuous load. |
Pinout & Package
SOT416 (SC-75) plastic surface-mounted package: 1.8 mm × 1.4 mm × 0.95 mm body, 3-lead, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | input (base) | Connected internally to R1; accepts logic-level input directly from MCU or gate output. |
| 2 | GND (emitter) | Emitter tied to system ground; serves as common reference for input and output paths. |
| 3 | output (collector) | Switched output node; sinks current to ground when active, suitable for low-side switching. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated R1 bias resistor | 10 kΩ ±30 % eliminates need for external base resistor, reducing component count and PCB area. |
| PNP RET topology | Single-input, emitter-grounded configuration simplifies schematic capture and layout for digital on/off control. |
| Low VCEsat | ≤ −150 mV ensures <150 µW power loss at 1 mA load, critical for ultra-low-power sensor nodes. |
| High hFE guarantee | ≥200 at −1 mA enables reliable switching with weak drive sources such as I²C bus pull-ups or low-current GPIOs. |
| SOT416 footprint | Small 1.8 × 1.4 mm outline supports high-density routing in wearables and compact IoT modules. |
Applications
| LED Indicator Control | Microcontroller GPIO Expansion |
|---|---|
Use Scenario: Driving status LEDs from 3.3 V MCU outputs with limited sink current capability. IC Role / Device Role / Timing Role: Low-side PNP switch sinking LED current to ground; operates in DC on/off mode. Use Value: Eliminates external base resistor and saves 1.2 mm² PCB area per channel versus discrete solution. |
Use Scenario: Expanding limited GPIO count to control multiple peripheral enable lines (e.g., sensors, regulators). IC Role / Device Role / Timing Role: Digital buffer/level shifter translating 1.8 V or 3.3 V logic to 5 V-compatible enable inputs. Use Value: Guaranteed hFE ≥200 ensures full saturation even with marginal drive strength, preventing partial turn-on failures. |
| Logic-Level Translation | Low-Power Sensor Interface |
Use Scenario: Converting open-drain I²C bus signals to active-low enable inputs for analog front-end ICs. IC Role / Device Role / Timing Role: Inverting level translator with fixed R1 bias; supports up to 400 kHz signal edges. Use Value: −150 mV VCEsat provides >3.15 V high-level margin at 3.3 V supply, improving noise immunity. |
Use Scenario: Enabling/disabling battery-powered environmental sensors during sleep cycles. IC Role / Device Role / Timing Role: Ultra-low-quiescent switch controlling VCC path to sensor IC; operates in static DC mode. Use Value: 100 nA ICBO and 1 µA ICEO minimize leakage-induced battery drain during deep sleep states. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC114TE,115 | NPN complement with identical SOT416 package, 10 kΩ R1, but opposite polarity and VCEO = +50 V. | Requires inverted logic drive and sourcing (not sinking) output configuration. | Select when circuit topology demands NPN low-side switching or compatibility with existing NPN-based designs. |
| BC857B,215 | Discrete PNP transistor (no built-in resistors); requires external 10 kΩ base resistor and occupies larger SOT23 footprint. | Offers higher VCEO (−45 V) and IC (−100 mA), but increases BOM count and layout complexity. | Choose when design flexibility for adjustable biasing or higher frequency operation (>100 MHz) is required. |
Compared with PDTC114TE,115, PDTA114TEF,115 provides native PNP sinking capability ideal for ground-referenced loads; versus BC857B,215, it reduces assembly cost and improves reliability by integrating the critical bias resistor in a smaller footprint.
Availability
PDTA114TEF,115 is available at Aetrix Electronics and suitable for LED indicator control, microcontroller GPIO expansion, logic-level translation, and low-power sensor interface applications requiring stable component supply and long-term industrial availability.
Supply support for PDTA114TEF,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on automotive, industrial, computing, consumer, and wearable markets.
The PDTA114TEF,115 belongs to Nexperia's PNP Resistor-Equipped Transistor (RET) family, engineered to simplify digital interface design by replacing two-component solutions with a single, optimized, space-saving device.
FAQ
What is the function of the R1 resistor in PDTA114TEF,115?
The R1 resistor in PDTA114TEF,115 is a 10 kΩ (7–13 kΩ range) integrated input bias resistor connected between pin 1 (base) and the internal transistor base. It enables direct connection to logic outputs without external components, ensuring proper base drive for saturation while eliminating layout and BOM overhead. This resistor is fundamental to the RET architecture of PDTA114TEF,115.
Does PDTA114TEF,115 have an internal R2 resistor?
No, PDTA114TEF,115 has R2 = open per its datasheet specification - only R1 is integrated. This distinguishes it from dual-resistor RET variants and makes it suitable for applications requiring simple input biasing without emitter feedback. The absence of R2 is a defined feature of the PDTA114TEF,115 part number within the PDTA114T series.
What is the maximum operating temperature for PDTA114TEF,115?
The junction temperature (Tj) limit for PDTA114TEF,115 is 150 °C, and the ambient temperature range is −65 °C to +150 °C. Its thermal resistance Rth(j-a) is 833 K/W on FR4 PCB, so at 100 mA output current and 25 °C ambient, junction temperature rise is ~83 °C - well within safe limits. This thermal performance is specified for the SOT416 package used by PDTA114TEF,115.
Can PDTA114TEF,115 replace BC857 in digital circuits?
Yes, PDTA114TEF,115 is positioned as a cost-saving alternative to the BC857 series in digital applications, per its official datasheet. It matches BC857's −50 V VCEO and −100 mA IO ratings while integrating the base resistor - reducing component count and pick-and-place steps. However, pinout differs: PDTA114TEF,115 uses SOT416 (1-2-3 = base-emitter-collector), whereas BC857 uses SOT23 (1-2-3 = emitter-base-collector).
What does the '115' suffix indicate in PDTA114TEF,115?
The '115' suffix in PDTA114TEF,115 denotes the packing method: 3,000 units per 8 mm tape-and-reel with 4 mm pitch, per Nexperia's ordering information table. It is not a revision code or temperature grade - it specifies logistics format. This packaging variant is standard for automated SMT assembly of PDTA114TEF,115.
PDTA114TEF,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-89, SOT-490
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- PNP - Pre-Biased
- Current - Collector (Ic) (Max):
- 100 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 10 kOhms
- Resistor - Emitter Base (R2):
- -
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 200 @ 1mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 150 mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-89
PDTA114TEF,115 FAQ
1.How can I place an order for PDTA114TEF,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PDTA114TEF,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PDTA114TEF,115 reliable?
The price and inventory of PDTA114TEF,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PDTA114TEF,115 is usually 5 days.
3.What payment methods are accepted for PDTA114TEF,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PDTA114TEF,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PDTA114TEF,115?
PDTA114TEF,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PDTA114TEF,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PDTA114TEF,115?
For technical support, including PDTA114TEF,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PDTA114TEF,115 requirements.
6.How does Aetrix verify that PDTA114TEF,115 is sourced from the original manufacturer or authorized distributors?
All PDTA114TEF,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTA114TEF,115 meets industry standards.
7.What is the process for return or replacement of PDTA114TEF,115?
All PDTA114TEF,115 units undergo pre-shipment inspection (PSI). If there is an issue with PDTA114TEF,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTA114TEF,115 part is unused and in its original packaging.
Return procedure for PDTA114TEF,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PDTA114TEF,115 Tags

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MUN5211T1G
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DTC043ZEBTL
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DTC114EKAT146
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DDTD113ZC-7-F
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DRDNB16W-7
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MMUN2211LT1G
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