Nexperia USA Inc. PDTA123YMB,315

Overview

PDTA123YMB from Nexperia is a PNP resistor-equipped transistor (RET) in a leadless DFN1006B-3 (SOT883B) package, designed for digital switching in space-constrained applications. It integrates R1 = 2.2 kΩ and R2/R1 = 4.5 ratio bias resistors, delivers −100 mA output current, exhibits VCEsat ≤ −150 mV at IC = −10 mA/IB = −0.5 mA, and is AEC-Q101 qualified for automotive use.

For engineers reviewing the PDTA123YMB datasheet, PDTA123YMB pinout, PDTA123YMB application, or PDTA123YMB equivalent, key selection criteria include its built-in bias network simplifying base drive, ultra-low 0.37 mm package height for thin mobile designs, −50 V VCEO rating, and verified performance across −40 °C to +150 °C junction temperature range.

Technical Context

This PNP RET integrates two on-die resistors-R1 (input bias) and R2 (base-emitter feedback)-to eliminate external base resistors and ensure predictable turn-on/turn-off behavior. Its internal topology fixes the base current path and stabilizes DC gain (hFE ≥ 35 at IC = −5 mA), reducing sensitivity to PCB layout variations.

The device operates as a saturated switch with guaranteed VI(on) ≤ −1.15 V at IC = −20 mA and VI(off) ≥ −0.75 V at IC = −100 µA, enabling direct interfacing with 1.8 V–5 V logic families without level-shifting. Thermal resistance Rth(j-a) = 500 K/W supports continuous operation up to Tamb = 125 °C when mounted on standard FR4.

Key Specifications

Pinout & Package

DFN1006B-3 (SOT883B) is a leadless, ultra-small surface-mount plastic package measuring 1.0 × 0.6 × 0.37 mm with three solderable terminals and no exposed thermal pad. Its low profile suits thin portable electronics and high-density PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.

Compared with PDTC123YMB, PDTA123YMB provides native high-side switching and avoids level inversion; versus EMH11T2R, it offers 27% smaller area and 26% lower height-critical for modern mobile form factors-while maintaining equivalent bias precision and thermal performance.

Availability

PDTA123YMB is available at Aetrix Electronics and suitable for automotive interior lighting, smartphone status indicators, and wearable device power control requiring stable component supply across long production lifecycles.

Supply support for PDTA123YMB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, spun off from NXP in 2017 and focused on high-volume, high-reliability components for automotive, industrial, and consumer markets.

This part belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to replace traditional transistor-resistor combinations in digital interface and peripheral driver applications with improved consistency and board-space efficiency.

FAQ

Is PDTA123YMB compatible with reflow soldering processes?

Yes, PDTA123YMB is qualified for lead-free reflow soldering per JEDEC J-STD-020. Its DFN1006B-3 package uses standard SnAgCu paste and follows the recommended reflow profile with peak temperature ≤ 260 °C and time above liquidus of 60–90 seconds. The footprint in Figure 11 of the datasheet must be strictly followed to prevent tombstoning.

What is the maximum allowable pulsed current for PDTA123YMB?

The peak collector current is rated at −100 mA for pulses ≤ 1 ms with duty cycle ≤ 10%. This limit is defined in Table 5 (Limiting Values) and assumes FR4 PCB mounting with single-sided copper. Exceeding this value risks thermal runaway due to the device's 500 K/W junction-to-ambient thermal resistance.

Does PDTA123YMB require external decoupling when used with MCU GPIOs?

No external decoupling capacitor is required for basic switching operation, as the integrated R1/R2 network provides inherent filtering. However, a 100 nF ceramic capacitor placed near the VCC pin of the driven load is recommended to suppress transient noise during switching edges, especially in mixed-signal environments.

How does the R2/R1 ratio affect switching behavior in PDTA123YMB?

The R2/R1 = 4.5 ratio sets the internal feedback gain that determines base current division and saturation depth. A higher ratio increases base shunting, improving turn-off speed but slightly raising VCEsat; this fixed ratio ensures consistent timing and gain across units without calibration, unlike discrete transistor-resistor combinations.