NXP Semiconductors PDTA144EK,115
- Part No.:
- PDTA144EK,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PDTA144EK,115.pdf
- Description:
- TRANS PREBIAS PNP 50V 0.1A SMT3
- Quantity:
- Payment:

- Shipping:

Inventory:6,470
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PDTA144EK,115 from NXP Semiconductors is a PNP resistor-equipped transistor with integrated 47 kΩ base bias resistors (R1 and R2), designed for general-purpose switching in compact surface-mount applications. It features −50 V VCEO, −100 mA IO, and SOT346 (SC-59) package, enabling simplified driver circuits in power management and logic interface boards.
For engineers reviewing the PDTA144EK,115 datasheet, PDTA144EK,115 pinout, PDTA144EK,115 application, or PDTA144EK,115 equivalent, key selection criteria include its built-in bias network, PNP polarity, −150 mV VCEsat at −10 mA/−0.5 mA drive, thermal resistance of 500 K/W, and compatibility with reflow-only soldering per JEDEC J-STD-020.
Technical Context
This device integrates two precision 47 kΩ resistors (R1 = base-to-emitter, R2 = base-to-collector) to configure a single-transistor inverter or switch without external bias components. Its PNP topology supports active-low control in level-shifting and load-switching configurations where emitter-follower or common-emitter operation is required.
Designed for ambient temperatures from −65 °C to +150 °C and junction temperatures up to 150 °C, the PDTA144EK,115 operates with −1.2 V typical Vi(off) and −1.6 V typical Vi(on), enabling reliable digital signal interpretation in mixed-voltage systems with rail-to-rail input tolerance from −40 V to +10 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −50 V - maximum safe collector-emitter voltage under open-base conditions, defining off-state blocking capability |
| IO (DC) | −100 mA - continuous output current rating, setting maximum load drive capacity in switching mode |
| R1 / R2 | 47 kΩ ±28% - matched internal bias resistors enabling fixed-current gain setup and eliminating external resistor placement |
| VCEsat | −150 mV max at IC = −10 mA / IB = −0.5 mA - low saturation voltage ensures minimal conduction loss in high-efficiency switches |
| Ptot | 250 mW at Tamb ≤ 25 °C - total power dissipation limit in SOT346 package, dictating thermal derating above ambient |
| Rth j-a | 500 K/W - junction-to-ambient thermal resistance, used to calculate temperature rise under steady-state load |
| Vi(on) | −3.0 to −1.6 V - input-on voltage range confirming reliable turn-on with standard TTL or CMOS logic low levels |
Pinout & Package
Package: SOT346 (TO-236AB, SC-59A), plastic surface-mounted, 3-lead package measuring 3.1 × 2.7 × 1.3 mm (L × W × H), optimized for automated pick-and-place and reflow soldering only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base | Internal connection to both R1 and R2; accepts logic-level input to enable transistor switching without external bias network |
| 2 | Emitter | Common reference terminal for PNP operation; connects to higher potential rail in high-side switch configurations |
| 3 | Collector | Output terminal carrying switched load current; referenced to lower potential in common-emitter arrangements |
Key Features
| Feature | Design Value |
|---|---|
| Built-in bias resistors (R1 = R2 = 47 kΩ) | Eliminates need for two external resistors, reducing BOM count and PCB area by ~2.5 mm² per instance |
| −150 mV VCEsat at rated current | Minimizes power loss in saturated switching, supporting >95% efficiency in 3.3 V–5 V logic-driven loads |
| Reflow-only soldering compatibility | Ensures manufacturability in modern SMT lines without wave or hand-soldering process risks |
| −40 V to +10 V input voltage tolerance | Permits direct interfacing with diverse logic families and transient-tolerant control signals |
| JEDEC-standard SOT346 footprint | Enables drop-in replacement with other SC-59A devices and supports legacy board reuse |
Applications
| Logic Level Shifter | Microcontroller GPIO Driver |
|---|---|
Use Scenario: Translating 1.8 V microcontroller outputs to control 5 V peripheral enable lines. IC Role / Device Role / Timing Role: PNP inverter stage providing active-low level translation with rail-compatible input swing. Use Value: Eliminates need for dual-supply translators or discrete resistor networks while maintaining <100 ns propagation delay. | Use Scenario: Driving LED indicators or small relays directly from MCU I/O pins with current limiting handled internally. IC Role / Device Role / Timing Role: Single-transistor load switch configured in common-emitter mode with built-in base bias. Use Value: Reduces component count by two resistors per channel and avoids GPIO current-limiting calculations. |
| Power Rail Enable Switch | Bus Termination Control |
Use Scenario: Enabling/disabling a 3.3 V subsystem supply using an active-low enable signal from system controller. IC Role / Device Role / Timing Role: High-side PNP switch controlling VCC path with fast turn-off via R2 pull-down action. Use Value: Achieves <1 µs turn-off time due to internal R2-assisted base discharge, improving power sequencing accuracy. | Use Scenario: Dynamically enabling 120 Ω RS-485 termination resistors only during active communication phases. IC Role / Device Role / Timing Role: Low-leakage switch isolating termination network when bus is idle. Use Value: ICEO < −1 µA at −30 V ensures <10 nA standby current, preserving signal integrity and reducing quiescent power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC144EK | NPN complement with identical R1/R2 values, SOT346 package, and matching pinout (1=base, 2=collector, 3=emitter) | Requires inverted logic control and sourcing rather than sinking current; suitable for low-side switching | Select PDTC144EK when circuit topology demands NPN configuration or ground-referenced load switching |
| EMZ7T2R | PNP RET with R1 = 47 kΩ, R2 = 47 kΩ, but in smaller SOT-723 (1.2 × 0.8 × 0.5 mm) package and −80 mW Ptot | Lower power handling limits use to sub-50 mA loads; requires tighter layout for thermal management | Choose EMZ7T2R only when board space is constrained and load current remains below 40 mA |
Compared with PDTC144EK and EMZ7T2R, the PDTA144EK,115 offers balanced performance for mid-current PNP switching with proven manufacturability in SOT346, making it optimal for cost-sensitive industrial controls and consumer electronics where reliability and reflow compatibility are critical.
Availability
PDTA144EK,115 is available at Aetrix Electronics and suitable for logic interface, GPIO expansion, and power rail enable applications requiring stable component supply across automotive infotainment, industrial PLC modules, and IoT sensor nodes.
Supply support for PDTA144EK,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The PDTA144EK,115 belongs to NXP's resistor-equipped transistor (RET) product line, engineered to reduce design complexity and assembly cost in digital interface and power control circuits.
FAQ
What is the pin configuration of the PDTA144EK,115?
The PDTA144EK,115 uses SOT346 package with pin 1 = base, pin 2 = emitter, and pin 3 = collector. This arrangement supports common-emitter and emitter-follower topologies without external bias components. The internal R1 and R2 resistors connect between base-emitter and base-collector respectively, enabling direct logic-level drive of the PDTA144EK,115.
Does the PDTA144EK,115 require external bias resistors?
No, the PDTA144EK,115 integrates two 47 kΩ bias resistors (R1 and R2) internally, eliminating the need for external base resistors in standard switching configurations. This simplifies schematic capture, reduces PCB footprint, and improves manufacturing yield. The internal resistor network is factory-trimmed and thermally coupled to the die, ensuring stable operation of the PDTA144EK,115 across temperature ranges.
What is the maximum operating temperature for the PDTA144EK,115?
The PDTA144EK,115 has a maximum junction temperature (Tj) of 150 °C and an operating ambient temperature range of −65 °C to +150 °C. Its thermal resistance Rth j-a is 500 K/W in free air, meaning a 125 mW power dissipation raises junction temperature by 62.5 K above ambient. Derating is required above 25 °C ambient to maintain safe operation of the PDTA144EK,115.
Can the PDTA144EK,115 be used in linear amplification?
The PDTA144EK,115 is characterized and qualified primarily for switching applications, with DC current gain (hFE) specified at VCE = −5 V and IC = −5 mA (min 80). While it can operate in active region, its built-in resistors limit bias flexibility and linearity. For analog amplification, discrete transistors without integrated resistors are recommended over the PDTA144EK,115.
Is the PDTA144EK,115 compatible with lead-free reflow processes?
Yes, the PDTA144EK,115 is qualified for lead-free reflow soldering per JEDEC J-STD-020, with peak temperature tolerance up to 260 °C. NXP specifies reflow as the only recommended soldering method-wave or hand soldering is not supported. This ensures consistent interconnect reliability and prevents damage to the internal resistor network in the PDTA144EK,115.
PDTA144EK,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- PNP - Pre-Biased
- Current - Collector (Ic) (Max):
- 100 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 47 kOhms
- Resistor - Emitter Base (R2):
- 47 kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 80 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 250 mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMT3; MPAK
PDTA144EK,115 FAQ
1.How can I place an order for PDTA144EK,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PDTA144EK,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PDTA144EK,115 reliable?
The price and inventory of PDTA144EK,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PDTA144EK,115 is usually 5 days.
3.What payment methods are accepted for PDTA144EK,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PDTA144EK,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PDTA144EK,115?
PDTA144EK,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PDTA144EK,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PDTA144EK,115?
For technical support, including PDTA144EK,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PDTA144EK,115 requirements.
6.How does Aetrix verify that PDTA144EK,115 is sourced from the original manufacturer or authorized distributors?
All PDTA144EK,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTA144EK,115 meets industry standards.
7.What is the process for return or replacement of PDTA144EK,115?
All PDTA144EK,115 units undergo pre-shipment inspection (PSI). If there is an issue with PDTA144EK,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTA144EK,115 part is unused and in its original packaging.
Return procedure for PDTA144EK,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PDTA144EK,115 Tags

-
MUN5211T1G
onsemi

-
DTC043ZEBTL
Rohm Semiconductor

-
DTC114EKAT146
Rohm Semiconductor

-
DDTD113ZC-7-F
Diodes Incorporated

-
DRDNB16W-7
Diodes Incorporated

-
PDTC114ET,215
Nexperia USA Inc.

-
PDTC143ZT,215
Nexperia USA Inc.

-
PDTC143ET,215
Nexperia USA Inc.

-
PDTC143XT,215
Nexperia USA Inc.

-
MMUN2211LT1G
onsemi

-
PDTC144ET,215
Nexperia USA Inc.

-
PDTC124ET,215
Nexperia USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
