NXP Semiconductors PDTA144WE,115
- Part No.:
- PDTA144WE,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- SC-75, SOT-416
- Datasheet:
-
PDTA144WE,115.pdf
- Description:
- TRANS PREBIAS PNP 50V 0.1A SC75
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PDTA144WE from Nexperia is a PNP resistor-equipped transistor with integrated bias resistors R1 = 47 kΩ and R2 = 22 kΩ, designed for general-purpose switching in low-power digital interface circuits. It features VCEO = −50 V, IO = −100 mA, and SOT416 (SC-75) surface-mount package, enabling compact load switching in portable logic-level translators.
For engineers reviewing the PDTA144WE datasheet, PDTA144WE pinout, PDTA144WE application, or PDTA144WE equivalent, key selection criteria include its built-in resistor ratio (R2/R1 ≈ 0.47), guaranteed Vi(off) (−1.7 to −1.2 V), and thermal resistance of 830 K/W in SOT416 - critical for thermally constrained PCB layouts.
Technical Context
This device integrates two precision thin-film resistors directly into a PNP bipolar die to eliminate external base bias components. Its input-off voltage (Vi(off)) and input-on voltage (Vi(on)) are specified at defined current thresholds (IC = −100 μA and −2 mA), ensuring predictable logic-level compatibility with 3.3 V and 5 V CMOS outputs.
The SOT416 package imposes strict thermal limits: Ptot = 150 mW at Tamb ≤ 25 °C and Rth(j-a) = 830 K/W, requiring careful copper pour design. Device operation is validated across −65 °C to +150 °C ambient, with junction temperature limited to 150 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −50 V: Maximum safe collector-emitter reverse voltage before breakdown in open-base configuration. |
| IO | −100 mA: Continuous DC output current capability without derating at 25 °C ambient. |
| R1 | 47 kΩ ±28%: Integrated base pull-up resistor enabling single-resistor drive from high-impedance sources. |
| R2/R1 ratio | 0.47: Fixed feedback ratio setting stable DC bias point and reducing sensitivity to β variation. |
| Vi(off) | −1.7 to −1.2 V: Input voltage range guaranteeing device cutoff at IC ≤ −100 μA, compatible with TTL/CMOS logic low. |
| VCE(sat) | ≤ −150 mV at IC = −10 mA / IB = −0.5 mA: Low saturation voltage ensures minimal power loss in active-switching mode. |
| hFE | ≥60 at VCE = −5 V, IC = −5 mA: Minimum DC current gain supporting reliable switching with modest base drive. |
Pinout & Package
SOT416 (SC-75) is a plastic surface-mounted package with 3 leads, body dimensions 1.6 × 0.8 × 0.55 mm, optimized for high-density routing and reflow-only assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base | Internal connection to R1–R2 node; accepts logic-level input; no external bias required. |
| 2 | Emitter | Common emitter terminal; tied to system ground or negative rail in typical high-side switch configuration. |
| 3 | Collector | Switched output node; connects to load and positive supply; handles up to −100 mA DC current. |
Key Features
| Feature | Design Value |
|---|---|
| Built-in R1/R2 bias network | Eliminates two external resistors, reducing BOM count and PCB area by ≥2.5 mm² in typical 3.3 V GPIO interface. |
| Guaranteed Vi(off) window | Ensures robust turn-off margin against noise or leakage when driven by weak-sourcing microcontroller pins. |
| Low VCE(sat) | Minimizes conduction loss in battery-powered applications: <0.15 V drop at 10 mA enables >95% efficiency in 3.3 V loads. |
| Thermal performance in SOT416 | Rth(j-a) = 830 K/W allows continuous −100 mA operation only with ≥20 mm² 1-oz copper pad; no heatsink needed below 30 mA. |
Applications
| LED Driver Circuit | Microcontroller GPIO Expander |
|---|---|
Use Scenario: Driving a 20 mA indicator LED from a 3.3 V MCU I/O pin with limited sink capability. IC Role / Device Role / Timing Role: High-side PNP switch controlling LED anode connection to VCC, with base driven by inverted MCU signal. Use Value: Built-in R1/R2 eliminates need for external pull-up/pull-down, reducing component count and layout complexity while maintaining guaranteed turn-on/off thresholds. | Use Scenario: Level-shifting and buffering a 1.8 V FPGA I/O signal to control a 5 V peripheral enable line. IC Role / Device Role / Timing Role: Logic-level translator providing inversion and voltage translation between mismatched supply domains. Use Value: Vi(on) = −2.7 V ensures reliable activation from 1.8 V logic high (−1.8 V relative to 5 V rail), with <150 mV saturation drop preserving noise margin. |
| Power Rail Sequencing | Push-Pull Output Stage |
Use Scenario: Enabling a secondary 3.3 V LDO only after primary 5 V rail stabilizes, using open-collector monitoring signal. IC Role / Device Role / Timing Role: Active-low enable switch activated by comparator output; provides clean, resistor-free gating of LDO EN pin. Use Value: Guaranteed Vi(off) ≤ −1.2 V prevents false triggering from comparator offset or supply ripple, improving system startup reliability. | Use Scenario: Constructing a complementary output stage with PDTC144WE (NPN complement) to drive bidirectional bus lines. IC Role / Device Role / Timing Role: PNP half of push-pull pair sourcing current during logic-high phase; matched R1/R2 values ensure symmetrical drive strength. Use Value: Identical resistor tolerances (±28%) and thermal characteristics between PDTA144WE and PDTC144WE minimize shoot-through risk and timing skew in bidirectional interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC144WE | NPN complement with identical R1/R2 values and SOT416 package; VCEO = +50 V, IO = +100 mA. | Used where source-switching topology is impractical; requires inverted logic drive and positive-rail referenced load. | Select PDTC144WE when driving loads connected to ground (low-side switch) or when matching NPN-based existing designs. |
| EMZ7T2R | PNP RET in SOT-723 (1.2 × 0.8 × 0.5 mm); R1 = 47 kΩ, R2 = 22 kΩ; VCEO = −50 V, but IO = −100 mA rated at Tj ≤ 150 °C only. | Smaller footprint (−35% area vs SOT416); higher thermal resistance (Rth(j-a) = 1000 K/W) demands stricter layout controls. | Choose EMZ7T2R only when board space is critical and thermal margin can be verified via simulation or testing. |
Compared with PDTC144WE and EMZ7T2R, PDTA144WE offers the best balance of proven thermal performance in SOT416, documented Vi(off)/Vi(on) windows, and long-term supply stability - making it preferred for industrial control I/O modules where reliability outweighs ultra-miniaturization.
Availability
PDTA144WE is available at Aetrix Electronics and suitable for LED driver circuits, microcontroller GPIO expansion, power rail sequencing, and push-pull output stages requiring stable component supply and consistent parametric performance across production batches.
Supply support for PDTA144WE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, formed in 2017 from the former NXP Standard Products division, with focus on automotive, industrial, computing, and consumer markets.
The PDTA144W series belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete transistor + dual-resistor configurations in cost-sensitive, space-constrained digital interface and switching applications.
FAQ
What is the pin configuration of PDTA144WE in the SOT416 package?
Pin 1 is Base, Pin 2 is Emitter, and Pin 3 is Collector - confirmed in the "Simplified outline, symbol and pinning" section of the official Nexperia datasheet. This configuration supports high-side switching where the emitter connects to VCC and the collector drives the load to ground. The PDTA144WE pinout eliminates ambiguity in PCB layout and ensures correct orientation during automated placement.
Does PDTA144WE require external bias resistors?
No, PDTA144WE integrates R1 = 47 kΩ and R2 = 22 kΩ internally, forming a complete base bias network. This eliminates the need for external resistors in standard switching applications, reducing bill-of-materials count and PCB area. The internal resistor ratio (R2/R1 ≈ 0.47) is laser-trimmed during manufacturing, ensuring consistent DC operating points across the PDTA144WE production lot.
What is the maximum continuous collector current for PDTA144WE?
The maximum continuous DC output current (IO) for PDTA144WE is −100 mA at Tamb ≤ 25 °C, as specified in the Quick Reference Data table. Derating applies above 25 °C ambient - for example, at 60 °C, usable current drops to approximately −65 mA due to thermal limits imposed by the SOT416 package's Rth(j-a) = 830 K/W. This value is measured under standardized test conditions and applies directly to PDTA144WE without additional qualification.
Can PDTA144WE be used in 1.8 V logic interface applications?
Yes, PDTA144WE supports 1.8 V logic interfaces via its Vi(on) specification of −2.7 V (typical) at IC = −2 mA and VCE = −0.3 V. When referenced to a 3.3 V or 5 V rail, a 1.8 V logic high presents −1.5 V or −3.2 V at the base, falling within the guaranteed turn-on window. This behavior is explicitly characterized in the datasheet's "Characteristics" table and applies to the exact PDTA144WE variant.
Is PDTA144WE RoHS compliant and halogen-free?
Yes, PDTA144WE complies with RoHS Directive 2011/65/EU and is halogen-free per Nexperia's material declarations. The device uses lead-free matte tin termination and green molding compound, meeting JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) requirements. Compliance documentation, including IMDS and IPC-1752 reports, is available for PDTA144WE through Nexperia's official product portal.
PDTA144WE,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-75, SOT-416
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- PNP - Pre-Biased
- Current - Collector (Ic) (Max):
- 100 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 47 kOhms
- Resistor - Emitter Base (R2):
- 22 kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 60 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 150 mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-75
PDTA144WE,115 FAQ
1.How can I place an order for PDTA144WE,115 through Aetrix?
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6.How does Aetrix verify that PDTA144WE,115 is sourced from the original manufacturer or authorized distributors?
All PDTA144WE,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTA144WE,115 meets industry standards.
7.What is the process for return or replacement of PDTA144WE,115?
All PDTA144WE,115 units undergo pre-shipment inspection (PSI). If there is an issue with PDTA144WE,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTA144WE,115 part is unused and in its original packaging.
Return procedure for PDTA144WE,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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