Nexperia USA Inc. PDTB113EUX

Overview

PDTB113EUX from Nexperia is a PNP resistor-equipped transistor (RET) in SOT323 (SC-70) package, designed for digital switching applications with built-in 1 kΩ input and 1 kΩ base-emitter bias resistors, −50 V V_CEO, −500 mA I_O, and AEC-Q101 qualification for automotive use.

For engineers reviewing the PDTB113EUX datasheet, PDTB113EUX pinout, PDTB113EUX application, or PDTB113EUX equivalent, this device serves as a space- and BOM-optimized replacement for discrete BJT + resistor networks in logic-level load switching, microcontroller I/O interfacing, and high-temperature industrial control circuits.

Technical Context

This RET integrates a PNP bipolar transistor with two monolithically embedded silicon resistors: R1 (input-to-base, 1 kΩ) and R2 (base-to-emitter, 1 kΩ), enabling direct connection to CMOS/TTL logic without external bias components. The R2/R1 ratio is tightly controlled at 0.9–1.1, ensuring predictable turn-on behavior.

It operates across −55 °C to +175 °C ambient, supports 300 mW power dissipation on FR4 single-layer PCBs, and delivers h_FE = 33 (min) at I_C = −50 mA, V_CE = −5 V - optimized for saturated switching rather than linear amplification.

Key Specifications

Pinout & Package

SOT323 (SC-70) plastic surface-mounted package: ultra-compact 3-pin outline measuring 2.2 mm × 1.35 mm × 0.95 mm, optimized for high-density PCB layouts and reflow-compatible assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PNP resistor-equipped transistor applications.

Compared with PDTB113ZUX, PDTB113EUX offers tighter R2/R1 matching and lower VI(on), enabling faster, more deterministic switching with standard logic levels; versus BC807-40, it trades external design freedom for guaranteed bias stability, reduced test points, and AEC-Q101 compliance out-of-box.

Availability

PDTB113EUX is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controller (PLC) I/O modules, and consumer appliance control systems requiring stable component supply, long lifecycle support, and AEC-Q101 assurance.

Supply support for PDTB113EUX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and consumer markets.

PDTB113EUX belongs to the PDTB1xxxU series of AEC-Q101-qualified resistor-equipped transistors, engineered specifically to replace discrete BJT-resistor combinations in space-constrained, high-reliability digital switching applications.

FAQ

What is the maximum allowable input voltage at Pin 1?

The absolute maximum input voltage (V_I) for PDTB113EUX is −10 V to +10 V, as specified in Table 6. Exceeding this range risks permanent damage to the integrated R1 resistor or base-emitter junction. For 3.3 V or 5 V logic interfaces, no level-shifting is needed - VI(on) is −1.0 to −1.8 V and VI(off) is −0.6 to −1.5 V, ensuring robust compatibility.

Can PDTB113EUX be used in linear amplifier configurations?

No - PDTB113EUX is optimized for saturated switching, not linear operation. Its h_FE is specified only at I_C = −50 mA and V_CE = −5 V, and the integrated resistors prevent independent bias control. Use standard BJTs like BC807-40 for amplification; this RET's design intent is digital load switching with minimal external components.

How does thermal performance differ between single-layer and 4-layer PCB mounting?

On FR4 single-layer PCBs, R_th(j-a) is 500 K/W (P_tot = 300 mW at T_amb = 25 °C); on 4-layer boards, it improves to 353 K/W (P_tot = 425 mW). This 41 % reduction in thermal resistance significantly extends safe operating area - critical for sustained −500 mA loads in compact enclosures where airflow is limited.

Is there a recommended footprint or soldering profile for SOT323?

Yes - Nexperia specifies a reflow footprint with 0.55 mm pad width, 0.6 mm length, and 1.325 mm center-to-center spacing (Fig 54). Reflow peak temperature must not exceed 260 °C for ≤ 10 s. Wave soldering requires the footprint in Fig 55 with 0.5 mm solder land width and preferred transport direction aligned with pin 1–3 axis to prevent tombstoning.