NXP Semiconductors PDTC115EEF,115
- Part No.:
- PDTC115EEF,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- SC-89, SOT-490
- Datasheet:
-
PDTC115EEF,115.pdf
- Description:
- TRANS PREBIAS NPN 50V SC89
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PDTC115EEF,115 from NXP Semiconductors is an NPN resistor-equipped transistor with integrated bias resistors R1 = 100 kΩ and R2 = 100 kΩ, rated for VCEO = 50 V and IO = 20 mA DC output current, used in general-purpose switching and interface circuits on compact PCBs.
For engineers reviewing the PDTC115EEF,115 datasheet, PDTC115EEF,115 pinout, PDTC115EEF,115 application, or PDTC115EEF,115 equivalent, this discrete device serves as a space-optimized, reduced-component-count alternative to discrete BJT + resistor networks in low-power digital logic interfacing and level translation.
Technical Context
This resistor-equipped transistor integrates two precision 100 kΩ bias resistors (R1 between base and input, R2 between base and emitter) to enable single-resistor drive operation without external components. Its internal configuration supports direct connection to CMOS/TTL outputs.
The device operates as a saturated switch with VCE(sat) ≤ 150 mV at IC = 5 mA / IB = 0.25 mA and exhibits hFE ≥ 80 at VCE = 5 V and IC = 5 mA, ensuring reliable turn-on under standard logic voltage levels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V - maximum collector-emitter voltage before breakdown; supports 3.3 V/5 V logic rail interfacing with margin. |
| IO (DC) | 20 mA - continuous output current capability; sufficient for driving LEDs, small relays, or logic inputs. |
| R1, R2 | 100 kΩ each - matched internal bias resistors eliminate need for external pull-up/pull-down components. |
| VCE(sat) | ≤150 mV at IC=5 mA - low saturation voltage minimizes power loss and ensures clean logic-low output. |
| hFE | ≥80 at VCE=5 V, IC=5 mA - high DC current gain enables robust switching with minimal drive current. |
| Vi(on) | 1.5 V (typ.) - input-on voltage threshold compatible with 1.8 V, 3.3 V, and 5 V logic families. |
| Ptot | 250 mW at Tamb ≤ 25 °C - thermal rating suitable for SOT490 package in standard reflow assembly. |
Pinout & Package
PDTC115EEF,115 is housed in a plastic surface-mounted SOT490 (SC-89) package measuring approximately 1.7 × 1.35 × 0.95 mm, optimized for high-density layouts and reflow soldering only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base | Internally connected to R1 (100 kΩ) and R2 (100 kΩ); accepts logic-level input signal directly. |
| 2 | Emitter | Common emitter node; referenced to ground or low-side return path in switching configurations. |
| 3 | Collector | Output node; sinks up to 20 mA when saturated; connects to load (e.g., LED anode, gate of downstream FET). |
Key Features
| Feature | Design Value |
|---|---|
| Built-in bias resistors | Eliminates two external 100 kΩ resistors, reducing BOM count and PCB footprint by ~2.5 mm². |
| Simplified drive interface | Accepts direct connection to CMOS/TTL outputs without level-shifting or current-limiting resistors. |
| Low VCE(sat) | Ensures <150 mV drop across collector-emitter during conduction, preserving voltage headroom in 3.3 V systems. |
| Thermal performance | Rth(j-a) = 500 K/W enables stable operation up to 150 °C junction temperature under defined mounting conditions. |
| Reflow-compatible packaging | SOT490 package qualified for lead-free reflow only-no hand-soldering or wave soldering recommended. |
Applications
| LED Driver Circuit | Microcontroller GPIO Interface |
|---|---|
Use Scenario: Driving indicator LEDs from 3.3 V microcontroller pins with current limiting. IC Role / Device Role / Timing Role: NPN switch configured in common-emitter mode, sinking LED cathode current to ground. Use Value: Integrated 100 kΩ base resistors allow direct GPIO connection without external components, saving layout area and assembly cost. |
Use Scenario: Level-shifting and buffering between 1.8 V FPGA I/O and 5 V peripheral enable lines. IC Role / Device Role / Timing Role: Digital interface translator providing logic-compatible output swing and noise immunity. Use Value: Vi(on) = 1.5 V (typ.) ensures reliable turn-on from 1.8 V logic, while VCEO = 50 V supports 5 V load side. |
| Inverter Stage | Push-Pull Input Conditioning |
Use Scenario: Inverting digital signal in battery-powered sensor node where component count must be minimized. IC Role / Device Role / Timing Role: Single-transistor inverter with built-in bias network replacing discrete BJT + two resistors. Use Value: Reduces bill-of-materials by two passive components and associated placement time, improving manufacturing yield. |
Use Scenario: Converting open-drain I²C bus signals to active-high enable inputs for PMICs or regulators. IC Role / Device Role / Timing Role: Active pull-up switch that provides fast rise time and controlled current sourcing. Use Value: hFE ≥ 80 and low VCE(sat) ensure rapid, low-loss transitions critical for I²C timing compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NPN resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC115EK | SOT346 (SC-59) package; larger footprint (2.7 × 1.7 mm vs. 1.7 × 1.35 mm); Ptot = 250 mW same rating. | Better thermal dissipation margin due to larger pad area; less suitable for ultra-dense layouts. | Select when board space allows and higher thermal reliability is prioritized over miniaturization. |
| PDTC115EU | SOT323 (SC-70) package; slightly smaller body (2.2 × 1.35 mm) but lower Ptot = 200 mW and Rth(j-a) = 625 K/W. | Higher thermal resistance limits sustained 20 mA operation in ambient > 50 °C without derating. | Choose only for very low-duty-cycle switching or when SOT323 footprint compatibility is required. |
Compared with PDTC115EEF,115, PDTC115EK offers better thermal handling in constrained airflow environments, while PDTC115EU trades thermal margin for marginally smaller size-neither is pin-compatible due to differing pin assignments (SOT490: Pin 1=Base, Pin 2=Emitter, Pin 3=Collector; SOT323/SOT346 use Pin 1=Base, Pin 2=Collector, Pin 3=Emitter), requiring PCB layout changes.
Availability
PDTC115EEF,115 is available at Aetrix Electronics and suitable for LED driver circuits, microcontroller GPIO interfacing, and inverter stages requiring stable component supply across industrial control, consumer electronics, and IoT edge devices.
Supply support for PDTC115EEF,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The PDTC115EEF,115 belongs to NXP's resistor-equipped transistor family designed to reduce component count and simplify digital interface design in space-constrained, cost-sensitive electronics.
FAQ
What is the pin configuration of PDTC115EEF,115?
PDTC115EEF,115 uses a SOT490 package with Pin 1 = Base, Pin 2 = Emitter, Pin 3 = Collector. This differs from standard SOT23/SOT323 pinouts and must be verified against the official NXP outline drawing to avoid PCB layout errors. The internal resistor network connects R1 between Pin 1 and input, and R2 between Pin 1 and Pin 2.
Can PDTC115EEF,115 replace a discrete BJT plus two 100 kΩ resistors?
Yes, PDTC115EEF,115 is functionally equivalent to an NPN transistor with 100 kΩ base-to-input (R1) and base-to-emitter (R2) resistors. It eliminates two passives and reduces layout area, but requires verifying that the SOT490 footprint and pinout match the target circuit's routing constraints.
What is the maximum operating temperature for PDTC115EEF,115?
The PDTC115EEF,115 has a maximum junction temperature (Tj) of 150 °C and an operating ambient temperature range of −65 °C to +150 °C. At 25 °C ambient, its total power dissipation is rated at 250 mW; derating is required above 25 °C per the specified thermal resistance of 500 K/W.
Is PDTC115EEF,115 compatible with lead-free reflow processes?
Yes, PDTC115EEF,115 is qualified for lead-free reflow soldering only, as stated in the datasheet. Wave soldering and hand soldering are not recommended. The SOT490 package meets JEDEC J-STD-020 moisture sensitivity level (MSL) requirements for standard reflow profiles.
Does PDTC115EEF,115 support 1.8 V logic input drive?
Yes, PDTC115EEF,115 has a typical input-on voltage (Vi(on)) of 1.5 V at IC = 1 mA, making it compatible with 1.8 V logic families. Its guaranteed minimum hFE of 80 at 5 V VCE and 5 mA IC ensures reliable saturation even with marginal drive current from low-voltage sources.
PDTC115EEF,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-89, SOT-490
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- NPN - Pre-Biased
- Current - Collector (Ic) (Max):
- 20 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 100 kOhms
- Resistor - Emitter Base (R2):
- 100 kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 80 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 250µA, 5mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 250 mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-89
PDTC115EEF,115 FAQ
1.How can I place an order for PDTC115EEF,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PDTC115EEF,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PDTC115EEF,115 reliable?
The price and inventory of PDTC115EEF,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PDTC115EEF,115 is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PDTC115EEF,115?
For technical support, including PDTC115EEF,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PDTC115EEF,115 requirements.
6.How does Aetrix verify that PDTC115EEF,115 is sourced from the original manufacturer or authorized distributors?
All PDTC115EEF,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTC115EEF,115 meets industry standards.
7.What is the process for return or replacement of PDTC115EEF,115?
All PDTC115EEF,115 units undergo pre-shipment inspection (PSI). If there is an issue with PDTC115EEF,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTC115EEF,115 part is unused and in its original packaging.
Return procedure for PDTC115EEF,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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