NXP Semiconductors PDTC115ES,126

Overview

PDTC115ES from NXP Semiconductors is an NPN resistor-equipped transistor in a through-hole SOT54 (TO-92) package, featuring integrated 100 kΩ base bias resistors R1 and R2, 50 V V_CEO, 20 mA DC output current, and 500 mW power dissipation at T_amb ≤ 25 °C - used for general-purpose switching in digital interface circuits and level translation.

For engineers reviewing the PDTC115ES datasheet, PDTC115ES pinout, PDTC115ES application, or PDTC115ES equivalent, key selection criteria include its built-in bias network eliminating external resistors, TO-92 through-hole compatibility for prototyping and legacy designs, guaranteed 80 minimum h_FE at 5 mA, and thermal resistance of 250 K/W in free air.

Technical Context

The PDTC115ES integrates two precision 100 kΩ resistors (R1 = base-to-V_IN, R2 = base-to-emitter) to configure a single-transistor digital switch with predictable turn-on/off thresholds. Its internal resistor ratio (0.8–1.2) ensures stable biasing across temperature and process variation.

Designed for DC-coupled logic-level interfacing, it operates with V_I(OFF) ≤ 0.5 V and V_I(ON) ≥ 3 V at specified test conditions, enabling direct connection to TTL and CMOS outputs without additional conditioning circuitry.

Key Specifications

Pinout & Package

PDTC115ES uses the plastic single-ended leaded (through-hole) SOT54 (TO-92) package, with standardized lead spacing (2.54 mm pitch), body dimensions 4.8 × 3.6 × 14.5 mm, and axial lead configuration suitable for wave soldering and manual assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NPN resistor-equipped transistor applications.

Compared with PDTC115ES, PDTC114ES offers lower input impedance and faster switching but reduced noise immunity, while PDTC123ES provides superior saturation performance at the cost of less symmetric biasing - both require layout verification due to differing resistor networks and gain profiles.

Availability

PDTC115ES is available at Aetrix Electronics and suitable for LED driver circuits, digital logic level shifters, relay driver interfaces, and inverter-based signal conditioning requiring stable component supply and long-term obsolescence management.

Supply support for PDTC115ES includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The PDTC115ES belongs to NXP's resistor-equipped transistor (RET) product line, designed to simplify discrete logic interface design by integrating bias resistors into standard transistor packages for cost-sensitive, space-constrained applications.

FAQ

What is the pin configuration of the PDTC115ES?

The PDTC115ES has a fixed three-pin TO-92 (SOT54) configuration: Pin 1 is Base (connected to internal R1 and R2), Pin 2 is Collector, and Pin 3 is Emitter. This arrangement is confirmed in the official NXP datasheet section "Simplified outline, symbol and pinning" and applies exclusively to the PDTC115ES variant - other members of the PDTC115E series use different pinouts.

Can PDTC115ES replace a standard 2N3904 with external bias resistors?

Yes, the PDTC115ES can replace a 2N3904 plus two 100 kΩ bias resistors in digital switching applications, provided the circuit relies on fixed-base biasing and does not require adjustable gain or variable threshold control. The PDTC115ES integrates those resistors internally, simplifying layout and reducing part count - but note that its guaranteed h_FE minimum (80) and V_CE(sat) (150 mV) differ from the 2N3904's typical values, so verify load current and voltage margins in the final PDTC115ES design.

What is the maximum operating temperature for PDTC115ES?

The PDTC115ES has a maximum junction temperature (T_j) of 150 °C and an operating ambient temperature range of −65 °C to +150 °C. At T_amb = 25 °C, its total power dissipation is rated at 500 mW; derating is required above 25 °C per the thermal resistance of 250 K/W. For continuous operation at 70 °C ambient, the usable power drops to approximately 300 mW - always confirm thermal performance in the actual PCB layout and airflow conditions for the PDTC115ES.

Does PDTC115ES support reflow soldering?

No - the PDTC115ES uses the through-hole SOT54 (TO-92) package, which is not compatible with reflow soldering processes. NXP explicitly states in the datasheet that reflow is only recommended for surface-mount variants (e.g., PDTC115ET in SOT23). For PDTC115ES, wave soldering or hand soldering is required; lead-free soldering must follow JEDEC J-STD-020 guidelines for through-hole components, with peak temperature not exceeding 260 °C for ≤ 10 seconds.

How does the resistor ratio affect PDTC115ES performance?

The PDTC115ES features a resistor ratio (R2/R1) of 1.0 ±0.2, meaning R1 and R2 are matched within 20%. This tight matching ensures stable DC biasing, predictable V_I(OFF) and V_I(ON) thresholds, and consistent turn-on/turn-off behavior across temperature and manufacturing lots - critical for reliable digital switching. Deviations outside this ratio would alter the effective base voltage divider, potentially causing incomplete turn-off or excessive base current, so the PDTC115ES leverages this controlled ratio to guarantee performance without external trimming.