Nexperia USA Inc. PDTC143EQCZ

Overview

PDTC143EQC from Nexperia is a 50 V, 100 mA NPN resistor-equipped transistor (RET) in a DFN1412D-3 (SOT8009) leadless SMD package with side-wettable flanks. It integrates 4.7 kΩ input and 4.7 kΩ base-emitter bias resistors, delivers 100 mA output current, exhibits 100 mV V_CE(sat) at I_C = 10 mA / I_B = 0.5 mA, and supports digital switching of IC inputs and low-power loads in space-constrained PCBs.

For engineers reviewing the PDTC143EQC datasheet, PDTC143EQC pinout, PDTC143EQC application, or PDTC143EQC equivalent, this part serves as a drop-in, component-count-reducing replacement for discrete BJT + resistor networks in logic-level interface and load control circuits-especially where AOI-compatible solder joints and sub-0.5 mm profile are required.

Technical Context

This RET implements a monolithic NPN transistor with two integrated precision thin-film resistors: R1 (4.7 kΩ) between base and input terminal, and R2 (4.7 kΩ) between base and emitter. The internal resistor ratio (R2/R1 = 1.0) ensures predictable turn-on/off thresholds and eliminates external biasing components.

Designed for digital switching, it operates with VI(on) = 1.9–2.5 V (at I_C = 20 mA) and VI(off) = 0.5–1.1 V (at I_C = 100 µA), enabling reliable interfacing with 3.3 V and 5 V logic families while maintaining low leakage (ICEO ≤ 5 µA at T_j = 150 °C).

Key Specifications

Pinout & Package

DFN1412D-3 (SOT8009) is a 3-terminal, leadless, surface-mount plastic package with side-wettable flanks, 0.8 mm pitch, and 0.48 mm body height-optimized for high-density routing and AOI-compatible reflow assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NPN resistor-equipped transistor applications.

Compared with PDTC114EQC, PDTC143EQC offers lower input threshold and higher drive capability for stronger logic families; compared with BC847B, it saves PCB area and eliminates resistor placement-critical for miniaturized, AOI-manufactured designs.

Availability

PDTC143EQC is available at Aetrix Electronics and suitable for industrial control panels, IoT sensor nodes, and consumer electronics requiring stable component supply, AOI-compatible assembly, and ultra-compact switching solutions.

Supply support for PDTC143EQC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors-including logic, discretes, MOSFETs, and ESD protection devices.

PDTC143EQC belongs to Nexperia's resistor-equipped transistor (RET) product line, engineered specifically to replace discrete BJT-resistor combinations in digital interface and load-switching applications-reducing design complexity and manufacturing cost.

FAQ

What is the maximum operating temperature for PDTC143EQC?

The PDTC143EQC has a maximum junction temperature (T_j) of 150 °C and an ambient operating range of −55 °C to +150 °C. Its thermal resistance R_th(j-a) is 348 K/W on standard FR4 (35 µm copper), meaning it can dissipate up to 360 mW at 25 °C ambient before reaching T_j = 150 °C.

Can PDTC143EQC be used with 1.8 V logic inputs?

No-PDTC143EQC requires a minimum VI(on) of 1.9 V (typical) to reliably saturate, and its VI(off) upper limit is 1.1 V. At 1.8 V, the device operates near the transition region with unpredictable gain and elevated V_CE(sat); use PDTC124EQC (VI(on) = 1.7 V typ.) or discrete solutions instead.

Is the DFN1412D-3 package compatible with standard reflow profiles?

Yes-the DFN1412D-3 (SOT8009) package is qualified for JEDEC J-STD-020 moisture sensitivity level 1 and supports standard lead-free reflow profiles (peak 260 °C). Its side-wettable flanks and recommended stencil thickness of 0.1 mm ensure robust solder joint formation under IPC-A-610 Class 2/3 requirements.

How does the built-in resistor ratio affect switching behavior?

The R2/R1 ratio of 1.0 (4.7 kΩ / 4.7 kΩ) sets a fixed base bias network that yields consistent VI(on) and VI(off) thresholds across process and temperature. This eliminates variability from hand-selected external resistors and ensures repeatable turn-on delay (<100 ns) and fall time in digital switching applications.