NXP Semiconductors PDTC144WK,115
- Part No.:
- PDTC144WK,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Single, Pre-Biased Bipolar Transistors
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PDTC144WK,115.pdf
- Description:
- TRANS PREBIAS NPN 50V 0.1A SMT3
- Quantity:
- Payment:

- Shipping:

Inventory:7,244
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Product details
Overview
PDTC144WK,115 from NXP Semiconductors is an NPN resistor-equipped transistor with integrated bias resistors R1 = 47 kΩ and R2 = 22 kΩ, rated for VCEO = 50 V and IO = 100 mA DC, housed in SOT346 (SC-59) package. It functions as a single-chip switch in digital logic interfaces, level translators, and LED drivers where simplified BOM and reduced PCB footprint are critical.
For engineers reviewing the PDTC144WK,115 datasheet, PDTC144WK,115 pinout, PDTC144WK,115 application, or PDTC144WK,115 equivalent, key selection criteria include its fixed internal resistor ratio (R2/R1 ≈ 0.47), guaranteed VCE(sat) ≤ 150 mV at IC = 10 mA / IB = 0.5 mA, thermal resistance of 500 K/W in free air, and compatibility with reflow-only soldering per JEDEC J-STD-020.
Technical Context
The PDTC144WK,115 integrates two precision thin-film resistors directly into the NPN die structure - R1 connected between base and input, R2 between base and emitter - enabling direct connection to CMOS/TTL logic without external bias components. Its current gain hFE ≥ 60 at VCE = 5 V and IC = 5 mA supports reliable saturation switching across industrial temperature range.
Designed for surface-mount assembly on FR4 PCBs, the device uses standard SOT346 leadframe construction with 1.3 mm × 1.0 mm body dimensions and specified mounting conditions per NXP's SOT346 outline. Thermal performance is characterized with Rth(j-a) = 500 K/W in free air, limiting continuous power dissipation to 250 mW at Tamb ≤ 25 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | 50 V maximum - ensures safe operation in 24 V control rails and 3.3/5 V logic interfacing with margin. |
| IO (DC) | 100 mA - supports driving LEDs, small relays, or logic gates without external current amplification. |
| R1 | 47 kΩ ±28% - sets input impedance and defines minimum drive current required for saturation. |
| R2 | 22 kΩ ±28% - stabilizes base voltage and improves noise immunity during off-state. |
| VCE(sat) | ≤150 mV at IC=10 mA/IB=0.5 mA - minimizes conduction loss and self-heating in high-duty-cycle switching. |
| hFE | ≥60 at VCE=5 V, IC=5 mA - guarantees sufficient current gain for predictable turn-on under defined bias conditions. |
| Tj max | 150 °C - enables operation in enclosed industrial enclosures with ambient up to +85 °C when derated. |
Pinout & Package
PDTC144WK,115 is supplied in the SOT346 (TO-236AB, SC-59A) plastic surface-mounted package: 3-lead, 1.3 mm × 1.0 mm × 0.95 mm body, gull-wing leads, JEDEC-compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base | Input node connected internally to R1 (47 kΩ) and R2 (22 kΩ); accepts logic-level signals directly. |
| 2 | Emitter | Common reference terminal; tied to ground or low-side return path in switch configurations. |
| 3 | Collector | Output node; sinks load current up to 100 mA with VCE(sat) ≤ 150 mV when properly biased. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated R1/R2 bias network | Eliminates 2 external resistors, reducing BOM count and layout area while ensuring consistent bias ratio (0.37–0.57). |
| Guaranteed VCE(sat) ≤ 150 mV | Enables low-loss switching in battery-powered or thermally constrained applications without heatsinking. |
| Reflow-solder compatible only | Ensures mechanical reliability and interconnect integrity per JEDEC J-STD-020, avoiding thermal damage during assembly. |
| 150 °C junction rating | Supports sustained operation in automotive under-hood or industrial motor-control environments with proper PCB copper pour. |
Applications
| LED Driver Circuit | Microcontroller GPIO Expander |
|---|---|
Use Scenario: Driving 20 mA indicator LEDs from 3.3 V MCU outputs with no external components. IC Role / Device Role / Timing Role: Single-stage NPN switch translating logic-high to LED cathode sink. Use Value: Reduces component count by two resistors per channel and eliminates manual resistor selection errors. | Use Scenario: Adding discrete output capability to resource-constrained microcontrollers lacking sufficient GPIO drive strength. IC Role / Device Role / Timing Role: Level-shifting and current-boosting interface between MCU I/O and external 5 V logic or sensors. Use Value: Enables direct connection to 5 V peripherals without level translators or discrete transistor+resistor stages. |
| Logic-Level Inverter | Low-Power Sensor Interface |
Use Scenario: Implementing non-inverting or inverting digital signal paths in compact sensor nodes. IC Role / Device Role / Timing Role: Active pull-down stage converting open-drain or weak-drive signals to robust CMOS-compatible outputs. Use Value: Provides sharp edge transitions and stable logic thresholds without external biasing networks. | Use Scenario: Conditioning analog sensor outputs (e.g., thermistor dividers) before ADC sampling in portable devices. IC Role / Device Role / Timing Role: Low-leakage switch isolating sensor bias paths during sleep mode to extend battery life. Use Value: ICEO ≤ 1 μA at 30 V ensures <100 nA standby current draw, critical for multi-year battery operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NPN resistor-equipped transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PDTC144ET,115 | SOT23 package (smaller footprint), same R1/R2 values and VCEO/IO ratings. | Higher thermal resistance (500 K/W vs. same), identical electrical behavior but tighter board space requirement. | Select when PCB real estate is constrained and thermal load remains below 150 mW. |
| PDTC124EK,115 | R1 = 22 kΩ, R2 = 47 kΩ - inverted resistor ratio yielding higher input sensitivity and lower Vi(on). | Optimized for 1.8 V/2.5 V logic families; requires verification of Vi(on) compatibility with host MCU. | Select when driving from low-voltage logic or needing faster turn-on with reduced input current. |
Compared with PDTC144WK,115, PDTC144ET,115 offers identical functionality in a smaller SOT23 package but with identical thermal limits, while PDTC124EK,115 provides complementary biasing for lower-voltage inputs - neither is pin-compatible, requiring layout revision for substitution.
Availability
PDTC144WK,115 is available at Aetrix Electronics and suitable for LED driver circuits, microcontroller GPIO expansion, logic-level inversion, and low-power sensor interface applications requiring stable component supply and long-term industrial availability.
Supply support for PDTC144WK,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The PDTC144WK,115 belongs to NXP's resistor-equipped transistor (RET) product line, designed to simplify digital interface design by integrating biasing resistors directly onto the transistor die for plug-and-play switching in space- and cost-sensitive applications.
FAQ
What is the pin configuration of PDTC144WK,115?
PDTC144WK,115 uses the SOT346 package with pin 1 = Base, pin 2 = Emitter, and pin 3 = Collector. This configuration is confirmed in the "Simplified outline, symbol and pinning" section of the official NXP datasheet (2004 Aug 17), and matches the standard SOT346 pinout for NPN RETs. The internal R1 connects pin 1 to the input, and R2 connects pin 1 to pin 2.
Does PDTC144WK,115 support through-hole mounting?
No, PDTC144WK,115 is exclusively a surface-mount device in the SOT346 package and does not support through-hole mounting. The PDTC144WS variant (SOT54/TO-92) is the through-hole option in the same family. Attempting to mount PDTC144WK,115 in a through-hole footprint will result in mechanical misalignment and solder joint failure.
What is the maximum operating temperature for PDTC144WK,115?
The PDTC144WK,115 has a maximum junction temperature (Tj) of 150 °C and an operating ambient temperature range of −65 °C to +150 °C. At Tamb = 25 °C, its total power dissipation is limited to 250 mW. Derating is required above 25 °C per the thermal resistance Rth(j-a) = 500 K/W specified in the datasheet.
Can PDTC144WK,115 replace a standard 2N3904 with external bias resistors?
Yes, PDTC144WK,115 can replace a 2N3904 plus two external bias resistors in switching applications where R1 = 47 kΩ and R2 = 22 kΩ match the required bias network. However, it is not a drop-in replacement for general-purpose amplification due to fixed internal resistors and lower hFE tolerance - verify Vi(on)/Vi(off) thresholds and saturation behavior in the target circuit.
Is PDTC144WK,115 RoHS compliant and halogen-free?
Yes, PDTC144WK,115 is RoHS compliant and halogen-free per NXP's product compliance documentation. The device carries the "115" suffix, which denotes lead-free (Pb-free) termination and compliance with EU RoHS Directive 2011/65/EU and JEDEC JS709B. Full material declarations are available via NXP's compliance portal using the full part number PDTC144WK,115.
PDTC144WK,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- NPN - Pre-Biased
- Current - Collector (Ic) (Max):
- 100 mA
- Voltage - Collector Emitter Breakdown (Max):
- 50 V
- Resistor - Base (R1):
- 47 kOhms
- Resistor - Emitter Base (R2):
- 22 kOhms
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 60 @ 5mA, 5V
- Vce Saturation (Max) @ Ib, Ic:
- 150mV @ 500µA, 10mA
- Current - Collector Cutoff (Max):
- 1µA
- Frequency - Transition:
- -
- Power - Max:
- 250 mW
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMT3; MPAK
PDTC144WK,115 FAQ
1.How can I place an order for PDTC144WK,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PDTC144WK,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PDTC144WK,115 reliable?
The price and inventory of PDTC144WK,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PDTC144WK,115 is usually 5 days.
3.What payment methods are accepted for PDTC144WK,115?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PDTC144WK,115?
PDTC144WK,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PDTC144WK,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PDTC144WK,115?
For technical support, including PDTC144WK,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PDTC144WK,115 requirements.
6.How does Aetrix verify that PDTC144WK,115 is sourced from the original manufacturer or authorized distributors?
All PDTC144WK,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PDTC144WK,115 meets industry standards.
7.What is the process for return or replacement of PDTC144WK,115?
All PDTC144WK,115 units undergo pre-shipment inspection (PSI). If there is an issue with PDTC144WK,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PDTC144WK,115 part is unused and in its original packaging.
Return procedure for PDTC144WK,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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