Infineon Technologies PEF 20470 H V1.3

Overview

PEF 20470 H V1.3 from Infineon Technologies is a programmable switching IC for time-division multiplexed (TDM) voice and data routing in digital telephony systems. It implements a 256×256 non-blocking time-slot interchanger with 8-bit parallel PCM interface, integrated analog PLL clock generator (APLL), and JTAG boundary-scan support. Designed for PBX and central office (CO) line cards, it supports subchannel, broadcast, multipoint, and bidirectional switching modes with hardware reset timing compliance per DS1 Rev. 1.3.

For engineers reviewing the PEF 20470 H V1.3 datasheet, PEF 20470 H V1.3 pinout, PEF 20470 H V1.3 application, or PEF 20470 H V1.3 equivalent, key selection criteria include TDM switching capacity, APLL jitter transfer performance, PCM interface timing compatibility with Intel/Motorola µP buses, and register-level configuration of connection types including 1-/2-/4-/8-bit subchannels.

Technical Context

The PEF 20470 H V1.3 integrates a Switching Factory with configurable connection granularity (1–8 bits), supporting minimum-delay and constant-delay switching paths. Its APLL accepts 2.048 MHz or 4.096 MHz reference input and generates synchronized 8.192 MHz, 16.384 MHz, and 32.768 MHz clocks with phase alignment capability for frame synchronization across multiple devices.

It features dual microprocessor interfaces (Intel/Siemens and Motorola modes), both multiplexed and de-multiplexed variants, plus an 8-bit local PCM bus supporting parallel mode operation. Configuration is performed via indirect register addressing using CMD1/CMD2 registers, while interrupt handling relies on ISTA1, IESTA1/IESTA2, and INTEM1/INTEM2 status/mask registers.

Key Specifications

Pinout & Package

PEF 20470 H V1.3 is housed in a 144-pin LQFP package (20 mm × 20 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per DS1 Rev. 1.3 Figure 3 and Section 2.2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TDM switching applications.

Compared with PEF 20450 MTSI, PEF 20470 H V1.3 reduces system-level clock design complexity by integrating APLL with phase alignment; compared with PEF 24470 MTSI-XL, it trades extended temperature rating and tighter jitter specs for lower unit cost and standard industrial qualification.

Availability

PEF 20470 H V1.3 is available at Aetrix Electronics and suitable for digital PBX line cards, VoIP gateway TDM aggregation, and central office multipoint conferencing requiring stable component supply and long-term lifecycle support.

Supply support for PEF 20470 H V1.3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive, and wired communications ICs, with headquarters in Munich.

The PEF series belongs to Infineon's Wired Communications product line, engineered specifically for carrier-grade TDM switching, clock recovery, and line-card integration in digital telephony infrastructure.

FAQ

What is the maximum supported PCM data rate for PEF 20470 H V1.3?

The device supports standard E1 (2.048 Mbps) and T1 (1.544 Mbps) PCM rates via its 8-bit parallel interface. Frame sync (PCM_FS) operates at 8 kHz, and bit clock is derived internally from the APLL at 2.048 MHz or 4.096 MHz reference inputs. No oversampling or fractional-N synthesis is implemented - all rates are integer multiples of the reference clock.

Does PEF 20470 H V1.3 support hot-swap or in-service reconfiguration?

No. The device requires a full hardware reset (≥100 ns pulse) to reload configuration registers and reinitialize the switching fabric. While individual connections can be established/released dynamically via command registers, global parameters like clock mode, interface polarity, and APLL settings are locked until reset. Live firmware updates without service interruption are not supported.

How does the APLL jitter transfer function impact system timing compliance?

The APLL exhibits –30 dB/octave roll-off below 100 Hz and –6 dB/octave above 1 kHz, meeting ITU-T G.823/G.824 wander and jitter requirements for primary rate interfaces. Measured jitter transfer peaks at –15 dB at 100 Hz, ensuring that upstream network jitter is attenuated before being distributed to downstream codecs and transceivers.

Can PEF 20470 H V1.3 operate without an external crystal?

Yes - CLKIN accepts either a 2.048 MHz or 4.096 MHz crystal (with load capacitance 12–20 pF) or a buffered CMOS clock signal. No internal oscillator is present; external timing source is mandatory for APLL operation. If no clock is applied, the device remains in reset and all outputs are tri-stated.