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Texas Instruments PGA112AIDGSR
- Part No.:
- PGA112AIDGSR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
PGA112AIDGSR.pdf
- Description:
- IC OPAMP PGA 1 CIRCUIT 10VSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,975
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Product details
Overview
PGA112AIDGSR from Texas Instruments is a zero-drift programmable gain amplifier (PGA) with integrated 2-channel analog multiplexer, SPI interface, and rail-to-rail input/output operation. It delivers 25 μV typical offset, 0.35 μV/°C drift, 12 nV/√Hz noise, binary gains up to 128, and operates from 2.2 V to 5.5 V supplies. It is used in precision sensor signal conditioning for e-metering and portable data acquisition.
For engineers reviewing the PGA112AIDGSR datasheet, PGA112AIDGSR pinout, PGA112AIDGSR application, or PGA112AIDGSR equivalent, key selection criteria include zero-drift performance at 125°C, SPI-controlled gain switching in <200 ns, dual-channel MUX support, internal calibration channels (GND/0.1VCAL/0.9VCAL/VREF), and separate AVDD/DVDD supplies for mixed-voltage ADC interfacing.
Technical Context
The PGA112AIDGSR implements a chopper-stabilized architecture with auto-zeroing to achieve near-zero input offset drift over temperature and time. Its two-input MUX selects between CH0 (also VCAL input) and CH1, feeding into a precision op-amp output stage with rail-to-rail swing and 10 kΩ//100 pF load drive capability.
SPI communication uses Mode 0,0 (CPOL = 0, CPHA = 0) at up to 10 MHz, with DIO bidirectional data line, SCLK clock, and active-low CS. Gain and channel selection are controlled via an 8-bit command register; no external configuration resistors or DACs are required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Offset Voltage | ±25 μV typical - enables direct measurement of mV-level sensor outputs without nulling circuitry |
| Offset Drift | 0.35 μV/°C typical - ensures stable DC accuracy across –40°C to 125°C industrial temperature range |
| Gain Options | Binary: 1, 2, 4, 8, 16, 32, 64, 128 - supports scalable amplification for varying sensor full-scale ranges |
| Input Noise Density | 12 nV/√Hz at f > 10 kHz - preserves SNR in high-bandwidth sensor interfaces (e.g., strain gauges, RTDs) |
| Supply Range | AVDD/DVDD = 2.2 V to 5.5 V - allows coexistence with 3.3 V microcontrollers and 5 V analog front-ends |
| Quiescent Current | 1.1 mA typical total - supports battery-powered operation with software shutdown reducing IQ to ≤4 μA |
| Channel Switch Time | 0.2 μs - enables rapid multiplexed sampling of multiple sensors without settling delay penalties |
Pinout & Package
PGA112AIDGSR is housed in a 10-pin VSSOP package (3.00 mm × 3.00 mm), optimized for space-constrained PCB layouts while maintaining thermal resistance of 98.3°C/W (junction-to-ambient).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 AVDD | Analog supply input | Provides power to amplifier core; must be bypassed with 0.1 μF ceramic capacitor near pin |
| 2 CH1 | Analog input channel 1 | High-impedance MUX input; supports ±10 mA fault current protection |
| 3 VCAL/CH0 | Calibration reference / analog input channel 0 | Dual-function pin: connects to external VCAL reference for system calibration or serves as primary sensor input |
| 4 VREF | Reference voltage input | Sets output common-mode level; requires ≥2 mA sourcing/sinking capability or connection to GND |
| 5 VOUT | Analog output | Rail-to-rail output capable of driving 5 mA; clamped to AVDD + 300 mV when AVDD < DVDD |
| 6 GND | Analog ground | Common return for analog signals and AVDD; must be separated from digital ground in mixed-signal layouts |
| 7 SCLK | SPI clock input | Accepts up to 10 MHz clock; timing-critical for gain/channel update latency |
| 8 DIO | SPI bidirectional data | Uses internal 10 μA pulldown; supports daisy-chain readback only in PGA116/PGA117 variants |
| 9 CS | SPI chip select | Active-low enable; CS high forces DIO to high-Z state for bus sharing |
| 10 DVDD | Digital/op-amp output supply | Defines logic levels and powers output stage; prevents ADC overvoltage when interfacing 3 V MCUs with 5 V PGA |
Key Features
| Feature | Design Value |
|---|---|
| Zero-drift architecture | Eliminates 1/f noise and long-term offset drift-critical for unattended metering systems requiring >10-year calibration stability |
| Four internal calibration channels | Enables on-the-fly system-level calibration using GND, 0.1VCAL, 0.9VCAL, and VREF-reduces need for external precision references |
| Rail-to-rail I/O | Maximizes dynamic range from 2.2 V supplies-enables full utilization of 12–16-bit ADCs without level-shifting circuitry |
| Separate AVDD and DVDD supplies | Isolates analog core from digital switching noise and avoids MCU ADC latch-up when PGA runs at 5 V and MCU at 3.3 V |
| Software shutdown mode | Reduces total supply current to ≤4 μA-extends battery life in handheld test equipment during idle periods |
Applications
| Remote e-Meter Reading | Portable Data Acquisition |
|---|---|
Use Scenario: High-accuracy energy measurement in smart electricity meters with CT/shunt-based current sensing and thermistor-based temperature compensation. IC Role / Device Role / Timing Role: Precision front-end PGA conditions low-level sensor outputs before feeding into a CDAC-based delta-sigma ADC. Use Value: 25 μV offset and 0.35 μV/°C drift ensure Class 0.2 meter accuracy across –25°C to 70°C operating range without periodic recalibration. | Use Scenario: Battery-powered handheld multimeter acquiring voltage, current, and resistance readings with auto-ranging. IC Role / Device Role / Timing Role: Configurable gain amplifier scales diverse input ranges (mV to V) to match ADC full-scale, with SPI-controlled channel/gain updates per measurement. Use Value: 128× gain and 12 nV/√Hz noise enable resolution of sub-μV signals from thermocouples, while 1.1 mA IQ extends runtime on coin-cell batteries. |
| PC-Based Signal Acquisition Systems | Programmable Logic Controllers |
Use Scenario: USB-connected DAQ modules for lab testing, capturing sensor data from accelerometers, pressure transducers, and load cells. IC Role / Device Role / Timing Role: Signal conditioner with MUX and programmable gain, interfaced via SPI to an MCU that bridges to PC host. Use Value: 200 ns gain switching time and 0.2 μs channel select time allow synchronized multi-sensor sampling at >10 kSPS without inter-channel crosstalk (>130 dB). | Use Scenario: Analog input modules in industrial PLCs accepting 4–20 mA, 0–10 V, and thermocouple inputs across multiple field channels. IC Role / Device Role / Timing Role: Precision gain stage preceding isolation and ADC stages; calibrated using internal VCAL channels to compensate for module-level drift. Use Value: Internal calibration channels (GND/0.1VCAL/0.9VCAL/VREF) reduce factory calibration time and improve long-term accuracy retention in harsh environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PGA113AIDGSR | Scope gain set (1, 2, 5, 10, 20, 50, 100, 200) instead of binary; identical pinout, package, and SPI interface | Better suited for applications requiring non-binary scaling (e.g., matching legacy sensor transfer functions or standard test equipment ranges) | Select PGA113AIDGSR when precise decade-based gain steps (e.g., ×10, ×100) are needed over binary progression |
| INA128UA | Fixed-gain (5–10,000) instrumentation amplifier; no MUX, no SPI, no internal calibration channels; SO-8 package | Used in simpler, lower-cost designs where gain is static and system calibration is performed externally | Choose INA128UA only if SPI control, multiplexing, and on-chip calibration are unnecessary and board space permits larger SO-8 footprint |
Compared with PGA113AIDGSR, PGA112AIDGSR offers finer binary gain resolution (×128 vs ×200 max) and lower THD+N at high gains, while INA128UA lacks digital configurability entirely-making PGA112AIDGSR optimal for automated, multi-sensor, self-calibrating systems.
Availability
PGA112AIDGSR is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and PC-based signal acquisition systems requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for PGA112AIDGSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision signal chain solutions.
The PGA112 belongs to TI's Zerø-Drift PGA product line, engineered specifically for high-accuracy sensor signal conditioning in utility metering, industrial automation, and portable instrumentation where DC stability and low noise are critical.
FAQ
What is the maximum SPI clock frequency supported by PGA112AIDGSR?
The PGA112AIDGSR supports SPI clock frequencies up to 10 MHz under recommended operating conditions (AVDD/DVDD = 2.2 V to 5.5 V). Timing parameters including tHI and tLO require minimum 40 ns pulse widths, and setup/hold times (tSU, tHD) are specified at 10 ns. For daisy-chain configurations-though not supported on PGA112AIDGSR-the limit reduces to 9.09 MHz due to cumulative propagation delays.
Does PGA112AIDGSR support hardware shutdown?
No, PGA112AIDGSR does not support hardware shutdown. It provides only software shutdown via SPI command, reducing total quiescent current to ≤4 μA. In contrast, the pin-compatible PGA116/PGA117 variants include an ENABLE pin for hardware shutdown. Designers requiring hardware control must select those variants or implement external supply gating.
How does the VCAL/CH0 pin function in PGA112AIDGSR calibration?
The VCAL/CH0 pin serves dual roles: as analog input channel 0 and as the external reference voltage source for internal calibration. When CAL2 or CAL3 channels are selected, VCAL is loaded with ~100 kΩ, enabling system-level offset/gain correction using ratios of 0.1VCAL and 0.9VCAL. This eliminates need for external precision dividers and improves temperature tracking versus fixed references.
Can PGA112AIDGSR drive a 10 kΩ load while maintaining rail-to-rail output swing?
Yes, PGA112AIDGSR maintains rail-to-rail output swing (GND + 50 mV to DVDD – 50 mV) when driving a 10 kΩ load with 100 pF capacitance, per electrical characteristics tables. At ±0.25 mA load current, output swing is specified from GND + 0.05 V to DVDD – 0.05 V. Performance degrades slightly at higher currents (e.g., ±5 mA yields GND + 0.25 V to DVDD – 0.25 V), but remains fully functional within datasheet limits.
What is the purpose of separate AVDD and DVDD supplies in PGA112AIDGSR?
Separate AVDD and DVDD supplies isolate the analog signal path from digital switching noise and prevent overvoltage damage to downstream 3 V ADCs. When DVDD = 3.3 V and AVDD = 5 V, the output stage is powered by DVDD, ensuring logic-compatible levels, while the analog core runs at higher voltage for improved SNR and headroom-without risking MCU input clamp diode conduction.
PGA112AIDGSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- Programmable Gain
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 8V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 10 MHz
- Current - Input Bias:
- 1.5 nA
- Voltage - Input Offset:
- 75 µV
- Current - Supply:
- 330µA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 2.2 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
PGA112AIDGSR FAQ
1.How can I place an order for PGA112AIDGSR through Aetrix?
Please submit a Request for Quotation (RFQ) for PGA112AIDGSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PGA112AIDGSR reliable?
The price and inventory of PGA112AIDGSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PGA112AIDGSR is usually 5 days.
3.What payment methods are accepted for PGA112AIDGSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PGA112AIDGSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PGA112AIDGSR?
PGA112AIDGSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PGA112AIDGSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PGA112AIDGSR?
For technical support, including PGA112AIDGSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PGA112AIDGSR requirements.
6.How does Aetrix verify that PGA112AIDGSR is sourced from the original manufacturer or authorized distributors?
All PGA112AIDGSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PGA112AIDGSR meets industry standards.
7.What is the process for return or replacement of PGA112AIDGSR?
All PGA112AIDGSR units undergo pre-shipment inspection (PSI). If there is an issue with PGA112AIDGSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PGA112AIDGSR part is unused and in its original packaging.
Return procedure for PGA112AIDGSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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