Texas Instruments PGA112AIDGST

Overview

PGA112AIDGST from Texas Instruments is a zero-drift programmable gain amplifier (PGA) with integrated 2-channel analog multiplexer, SPI interface, and rail-to-rail input/output. It delivers binary gain settings (1–128), 25 μV typical offset, 0.35 μV/°C drift, 12 nV/√Hz noise, and operates from 2.2 V to 5.5 V supplies. It is used in precision sensor signal conditioning for e-metering and portable data acquisition.

For engineers reviewing the PGA112AIDGST datasheet, PGA112AIDGST pinout, PGA112AIDGST application, or PGA112AIDGST equivalent, key selection criteria include its zero-drift architecture, dual-input MUX, SPI-controlled gain switching (200 ns), internal calibration channels (GND/0.1VCAL/0.9VCAL/VREF), and VSSOP-10 package compatibility with mixed-voltage AVDD/DVDD systems.

Technical Context

The PGA112AIDGST implements a chopper-stabilized zero-drift amplifier core with auto-zeroing, enabling ultra-low offset and drift over temperature. Its 2-channel MUX selects between CH0 (also VCAL input) and CH1, feeding into a digitally programmable gain stage controlled via 3-wire SPI (SCLK, DIO, CS) at up to 10 MHz.

Gain configuration uses an internal command register; binary gains (1, 2, 4, ..., 128) are selected by 3-bit code. The device supports system-level calibration via four dedicated internal channels tied to GND, 0.1×VCAL, 0.9×VCAL, and VREF - all accessible without external switches or routing.

Key Specifications

Pinout & Package

The PGA112AIDGST is housed in a 10-pin VSSOP package (3.00 mm × 3.00 mm), optimized for space-constrained PCB layouts while maintaining thermal performance (θ_JA = 98.3°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable gain amplifier applications.

Compared with PGA113AIDGST and INA128UA, the PGA112AIDGST uniquely combines binary programmability, integrated MUX, SPI interface, and on-die calibration in a 10-pin VSSOP-enabling compact, self-calibrating sensor interfaces without external support components.

Availability

PGA112AIDGST is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and PC-based signal acquisition systems requiring stable component supply and long-term manufacturability.

Supply support for PGA112AIDGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision amplifiers, data converters, and power management ICs.

The PGA112AIDGST belongs to TI's Zerø-Drift PGA product line, engineered for high-accuracy sensor signal conditioning in energy metering, industrial automation, and portable test equipment where offset stability and low noise are critical.

FAQ

What is the maximum SPI clock frequency supported by the PGA112AIDGST?

The PGA112AIDGST supports SPI clock frequencies up to 10 MHz under recommended operating conditions (AVDD/DVDD = 2.2 V to 5.5 V). Timing parameters including t_HI, t_LO, setup, and hold times are specified to ensure reliable communication at this rate. Exceeding 10 MHz may violate timing margins and cause command corruption or incomplete register updates in the PGA112AIDGST.

How does the PGA112AIDGST handle system-level calibration?

The PGA112AIDGST provides four internal calibration channels connected to GND, 0.1×VCAL, 0.9×VCAL, and VREF. When CAL2 or CAL3 is selected, VCAL/CH0 is loaded with ~100 kΩ, allowing precise ratio-based calibration. This eliminates external switches and reduces PCB area, enabling automated two-point calibration routines directly within firmware controlling the PGA112AIDGST.

Can the PGA112AIDGST operate with different analog and digital supply voltages?

Yes, the PGA112AIDGST supports independent AVDD (2.2 V to 5.5 V) and DVDD (2.2 V to 5.5 V) supplies. This allows interfacing with 3 V microcontrollers while powering the analog front-end from 5 V - preventing overvoltage on ADC inputs and avoiding lockup conditions. The PGA112AIDGST output is clamped to AVDD + 300 mV when AVDD < DVDD, ensuring safe operation.

What is the output drive capability of the PGA112AIDGST?

The PGA112AIDGST delivers ±5 mA output current while maintaining rail-to-rail swing (GND + 0.25 V to DVDD – 0.25 V). Short-circuit current is rated at –30/+60 mA. For capacitive loads, it drives up to 100 pF directly; larger loads require external isolation or buffering to maintain stability and settling performance in the PGA112AIDGST.

Does the PGA112AIDGST include power-on reset functionality?

Yes, the PGA112AIDGST incorporates an internal power-on reset (POR) circuit that disables the digital interface and initializes the command register to default values until DVDD exceeds 1.6 V. POR trip voltage is guaranteed at 1.6 V minimum, with power-up time of 40 μs and power-down time of 5 μs. This ensures deterministic startup behavior and prevents spurious gain changes during power ramp in the PGA112AIDGST.