Texas Instruments PGA112AIDGSTG4

Overview

PGA112AIDGSTG4 from Texas Instruments is a zero-drift programmable gain amplifier (PGA) with integrated 2-channel analog multiplexer, SPI interface, and rail-to-rail input/output operation. It delivers 25 μV typical offset, 0.35 μV/°C typical drift, 12 nV/√Hz input voltage noise, binary gain options up to 128, and operates from 2.2 V to 5.5 V supplies. It is used in precision sensor signal conditioning for e-metering and portable data acquisition systems.

For engineers reviewing the PGA112AIDGSTG4 datasheet, PGA112AIDGSTG4 pinout, PGA112AIDGSTG4 application, or PGA112AIDGSTG4 equivalent, key selection criteria include its zero-drift architecture, SPI-configurable gain switching (200 ns), dual-input MUX, internal calibration channels (GND/0.1VCAL/0.9VCAL/VREF), and separate AVDD/DVDD supplies enabling mixed-voltage interfacing with microcontrollers like MSP430.

Technical Context

The PGA112AIDGSTG4 implements a chopper-stabilized zero-drift amplifier core with auto-zeroing, enabling ultra-low offset and drift over temperature. Its 2-channel MUX selects between CH0 (also VCAL input) and CH1, feeding into a digitally programmable gain stage controlled via 3-wire SPI (SCLK, DIO, CS) at up to 10 MHz.

It features four internal calibration channels tied to GND, 0.1VCAL, 0.9VCAL, and VREF - allowing system-level offset/gain calibration without external components. The device supports software shutdown (IQ ≤4 μA) and operates across –40°C to +125°C with rail-to-rail output swing down to 50 mV from supply rails.

Key Specifications

Pinout & Package

PGA112AIDGSTG4 is housed in a 10-pin VSSOP package (3.00 mm × 3.00 mm), optimized for space-constrained PCB layouts while maintaining thermal performance (θJA = 98.3°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable gain amplifier applications.

Compared with PGA113AIDGST, PGA112AIDGSTG4 offers tighter binary gain steps ideal for digital control loops; versus AD8253ARMZ, it trades bandwidth for lower noise, zero-drift stability, and integrated calibration-reducing system-level calibration effort and component count.

Availability

PGA112AIDGSTG4 is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and PC-based signal acquisition systems requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for PGA112AIDGSTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision signal chain solutions.

PGA112AIDGSTG4 belongs to TI's Zerø-Drift PGA product line, designed specifically for high-accuracy sensor signal conditioning in energy metering, industrial automation, and portable instrumentation where offset, drift, and noise directly impact measurement integrity.

FAQ

What is the maximum SPI clock frequency supported by PGA112AIDGSTG4?

The PGA112AIDGSTG4 supports SPI clock frequencies up to 10 MHz under recommended operating conditions (AVDD/DVDD = 2.2 V to 5.5 V). Timing parameters including tHI and tLO require minimum 40 ns pulse width, and setup/hold times (tSU/tHD) are specified at 10 ns. Exceeding 10 MHz may violate timing margins and cause communication errors in the PGA112AIDGSTG4 SPI interface.

Does PGA112AIDGSTG4 support hardware shutdown?

No, PGA112AIDGSTG4 does not support hardware shutdown. It provides only software-controlled shutdown via SPI command, reducing total quiescent current to ≤4 μA. In contrast, the pin-compatible PGA116/PGA117 variants include an ENABLE pin for hardware shutdown. For designs requiring hardware-initiated low-power mode, PGA112AIDGSTG4 must be paired with a system-level controller to assert shutdown via SPI before power removal.

Can PGA112AIDGSTG4 drive an ADC input directly?

Yes, PGA112AIDGSTG4 is explicitly optimized for driving CDAC-based ADCs. Its rail-to-rail output swing (down to 50 mV from rails), low output impedance, and fast settling time (≤1.2 μs for 0.001% accuracy at G=1) ensure accurate signal transfer. When AVDD < DVDD, VOUT is clamped to AVDD + 300 mV - preventing overvoltage damage to 3 V ADC inputs powered from DVDD, making PGA112AIDGSTG4 suitable for mixed-supply interfacing.

What is the purpose of the VCAL/CH0 pin on PGA112AIDGSTG4?

The VCAL/CH0 pin serves dual functions: it is the primary analog input channel (CH0) and the external reference voltage input (VCAL) for the device's internal calibration system. When CAL2 or CAL3 channels are selected, VCAL/CH0 is loaded with ~100 kΩ; otherwise, it presents high impedance. Connecting a stable, low-impedance reference to VCAL/CH0 enables use of the four internal calibration channels (GND, 0.1VCAL, 0.9VCAL, VREF) - eliminating need for external calibration DACs or resistors in the PGA112AIDGSTG4 signal path.

How does PGA112AIDGSTG4 handle overvoltage on its input pins?

PGA112AIDGSTG4 input terminals are diode-clamped to AVDD and GND. The absolute maximum rating allows input voltages from GND – 0.5 V to AVDD + 0.5 V. Inputs exceeding this range must be current-limited to ≤10 mA using external series resistors to prevent permanent damage. The device guarantees no output phase reversal for inputs within GND – 0.3 V to AVDD + 0.3 V, preserving signal polarity integrity during transient overvoltage events in the PGA112AIDGSTG4 front-end.